Clock Signal Driver Replica Feedback for Voltage-Stable Timing
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Solution Overview
Problem
As the size of metal oxide semiconductor (MOS) transistors in clock signal drivers decreases, the delay of clock signals becomes more sensitive to changes in power supply voltages and temperature, necessitating improved control of timing to reduce susceptibility.
Innovation Solution
A clock signal driver with a driver circuit and a replica circuit, along with a delay control circuit, generates an output clock signal with constant timing by compensating for voltage fluctuations using a delay control signal based on a replica clock signal, independent of power supply voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the size of MOS transistors in clock signal drivers decreases, then the operating speed and integration density improve, but the delay of clock signals becomes more sensitive to changes in power supply voltages and temperature
Solution Approach 1:
The patent creates a replica circuit that is identical to the main driver circuit, including the same MOS transistor structure. This replica circuit generates a replica clock signal that experiences the same voltage and temperature-induced delays as the actual output clock signal. By monitoring the replica circuit's performance, the system can accurately measure delay changes without affecting the main circuit's operation, enabling precise compensation of timing variations.
Solution Approach 2:
The patent implements a feedback mechanism where the delay control circuit continuously monitors the replica clock signal and compares it against reference timing. Based on this feedback, the circuit dynamically adjusts delay control signals to compensate for voltage and temperature-induced delays. This closed-loop system ensures that timing variations are detected and corrected in real-time, maintaining stable output timing despite changes in operating conditions.
2Productivity
If the size of MOS transistors decreases, then device integration and speed improve, but control of timing becomes more difficult due to voltage and temperature sensitivity
Solution Approach 1:
The replica circuit provides a simplified model of the main driver circuit that can be easily monitored and controlled. By copying the same transistor structure and circuit topology, the patent enables straightforward measurement and control of delay characteristics without adding complex monitoring infrastructure to the main circuit itself.
Solution Approach 2:
The patent separates the timing control function into a dedicated delay control circuit that operates independently from the main driver circuit. This segmentation allows the timing control logic to be optimized separately, using the replica circuit for measurement and reference, while the main circuit focuses on signal generation. The delay control circuit receives delay control signals and independently adjusts timing parameters.
3Reliability
If delay control is added to compensate for voltage changes, then timing stability improves, but device complexity increases
Solution Approach 1:
The replica circuit serves as an identical copy of the main driver circuit, providing a parallel path for timing measurement and control. This copy allows the delay control circuit to monitor and adjust timing without interfering with the main signal generation path, enabling stable timing control while keeping the added complexity isolated to the replica and control circuits only.
Solution Approach 2:
The replica circuit serves multiple functions: it acts as a timing reference, a delay measurement device, and a control feedback source. By making the replica circuit multi-functional, the patent reduces the need for separate dedicated components for each function, thereby limiting the increase in overall device complexity while achieving robust timing stability.
Data Source
AI summary
A clock signal driver includes a driver circuit configured generate an output clock signal in response to a combination of an input clock signal, a delay control signal and a power supply voltage. The driver circuit includes a main driver circuit, which is configured to generate the output clock signal in response to the input clock signal, and a replica circuit having a structure equivalent to the main driver circuit; the replica circuit is configured to generate a replica clock signal, which is equivalent to the output clock signal, in response to the input clock signal. A delay control circuit is also provided and is responsive to the replica clock signal. The delay control circuit is configured to generate the delay control signal to correct a delay change in the output clock signal, which is caused by a change in voltage level of the power supply voltage.