Differential Clock Driver With Half-Swing Capacitive Switching
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Solution Overview
Problem
Differential clock drivers face bandwidth restrictions due to supply voltage charge to zero voltage discharge, requiring a compromise between clock speed, signal quality, and power consumption when using capacitive coupling for high data or clock rate interconnection.
Innovation Solution
A clock driver circuit design featuring complementary transistors with split-level charging/discharging capacitors, allowing for faster output response times and reduced power consumption by limiting the discharge voltage range to half the supply potential, thereby optimizing clock speed and signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If prior art differential clock drivers charge capacitors from supply voltage to zero voltage, then the capacitors can be fully charged, but the bandwidth is restricted and power consumption increases
Solution Approach 1:
The capacitor charging range is segmented into two halves: from 0V to VDD/2 and from VDD/2 to VDD. This segmentation allows the capacitors to be charged only to half the supply voltage in each transition, reducing the voltage swing and thereby reducing power consumption while maintaining adequate signal levels for clock distribution.
Solution Approach 2:
The patent changes the voltage parameter by introducing a mid-rail voltage level (VDD/2) as the target charge voltage instead of the traditional full supply voltage (VDD). This parameter change reduces the voltage swing amplitude, which directly reduces the energy consumed during charging and discharging cycles, while still maintaining sufficient signal integrity for clock distribution.
2Speed
If prior art differential clock drivers use full supply voltage swing, then signal quality is maintained, but output response time increases and clock speed is limited
Solution Approach 1:
The patent changes the voltage swing parameter from full supply voltage (VDD) to half supply voltage (VDD/2). This parameter change reduces the charging time constant and increases the output response time, enabling higher clock speeds. The differential nature of the signaling maintains signal quality even with reduced voltage swing.
Solution Approach 2:
The patent employs periodic toggling between two voltage states (0V to VDD/2 and VDD/2 to VDD) rather than continuous full-range charging. This periodic action with reduced amplitude enables faster switching cycles, increasing clock speed while maintaining sufficient signal transitions for reliable detection.
3Speed
If prior art differential clock drivers increase peak output currents, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The patent segments the voltage swing into smaller increments (half the original range), which reduces the peak current required to charge and discharge the coupling capacitors. The segmented charging approach maintains adequate bandwidth by ensuring sufficient voltage transitions occur within each clock cycle, while reducing the power consumption associated with high peak currents.
Data Source
AI summary
Clock driver circuit having upper and lower transistors1 and upper and lower transistors2. Voltage node1 coupled to electrodes of upper transistor1 and upper transistor2. Voltage node2 coupled to electrodes of lower transistor1 and lower transistor2. Coupling transistor1 couples another electrode of upper transistor1 to another electrode of lower transistor2. Coupling transistor2 couples another electrode of upper transistor2 to another electrode of lower transistor1. Two series1 capacitors couple the another electrode of upper transistor1 to the another electrode of lower transistor1. Two series2 capacitors couple the another electrode of upper transistor2 to the another electrode of lower transistor2. Node intermediate the two series2 capacitors provides in-phase clock output. Node intermediate the two series1 capacitors provides anti-phase clock output. In-phase clock input is coupled to control inputs of upper transistor1, coupling transistor1 and lower transistor1. Anti-phase clock input is coupled to control inputs of upper transistor2, coupling transistor2 and lower transistor2.