Clock Driver Circuit With Feedback and Edge-Slope Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock driver circuits face challenges in reducing clock jitter while maintaining low power consumption and avoiding excessive load capacitance, as increasing gain or transistor size leads to increased power consumption and capacitance.
Innovation Solution
The proposed clock driver circuit incorporates a dual-stage differential amplifier input stage with a common mode negative feedback loop and a double-ended to single-ended conversion stage with a branch circuit to enhance edge slope, reducing clock jitter without increasing power consumption or load capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gain of the first stage differential amplifier is increased to reduce clock jitter, then the clock jitter is reduced, but the power consumption increases
Solution Approach 1:
The clock driver circuit is divided into three functional stages: first stage differential amplifier, second stage differential amplifier, and output buffer. Each stage contributes differently to signal amplification and jitter reduction, allowing optimization of power consumption at each stage while achieving overall low jitter performance.
Solution Approach 2:
The patent optimizes the transistor width-to-length ratios and bias currents in each stage to achieve the desired gain and jitter performance. By carefully selecting device parameters such as W/L ratios of M1-M4 transistors and bias current values, the circuit achieves low jitter without excessive power consumption.
2Reliability
If the tail current of the second stage or transistor size is increased to reduce clock jitter, then the clock jitter is reduced, but the load capacitance increases
Solution Approach 1:
The circuit is segmented into multiple stages with the output buffer stage specifically designed to drive large capacitive loads. The buffer stage uses large-sized transistors (M7-M10) to provide high current driving capability, allowing the previous stages to operate with smaller devices and lower capacitance.
Solution Approach 2:
The second stage differential amplifier acts as an intermediary between the first stage and the output buffer. It provides additional gain and signal conditioning, allowing the output buffer to focus on driving the capacitive load rather than providing both gain and drive capability.
3Reliability
If the clock slope is increased to reduce clock jitter, then the clock jitter is reduced, but the power consumption increases
Solution Approach 1:
The first and second stage differential amplifiers perform preliminary signal conditioning and amplification before the signal reaches the output buffer. By establishing a strong, well-conditioned signal early in the chain, the output buffer can achieve fast edges with moderate current, reducing overall power consumption while maintaining low jitter.
Solution Approach 2:
The patent carefully selects the W/L ratios of transistors in each stage and optimizes bias currents to achieve the desired slew rate and edge slope. The output buffer uses appropriately sized transistors to provide fast edges without excessive current draw, balancing power consumption and jitter performance.
Data Source
AI summary
A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.