Clock Driver Gating for Low-Skew Time-Interleaved DACs
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Solution Overview
Problem
High bandwidth communication systems face challenges in achieving high-speed digital-to-analog conversion due to time skew between sub-DACs in time-interleaved DACs, which degrades image attenuation and interleaving operations, and existing calibration techniques are complex, power-intensive, and area-consuming.
Innovation Solution
The implementation of clock gating circuits that generate clock signals with low time skew without the need for duty cycle correction blocks or calibration, using clock dividing circuits and clock gating circuits to gate input clock signals and generate drive clock signals for sub-DACs, ensuring 180-degree phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved DACs are used to achieve high-speed digital-to-analog conversion, then conversion speed is improved, but time skew between sub-DACs degrades image attenuation and interleaving operations
Solution Approach 1:
The patent divides the clock signal distribution into separate paths for each sub-DAC, with each path having its own clock gating circuit. This segmentation allows independent control of clock signals to each sub-DAC, enabling precise timing alignment and reducing time skew between interleaved converters.
Solution Approach 2:
The patent implements preliminary phase alignment of clock signals before they reach the sub-DACs. By pre-adjusting the phase of clock signals through dedicated gating circuits, the system ensures that all sub-DACs are synchronized before conversion begins, preventing time skew degradation of image attenuation.
2Manufacturing precision
If complex calibration techniques are implemented to correct time skew, then time alignment precision is improved, but device complexity, power consumption, and area increase
Solution Approach 1:
The patent implements a self-aligning clock distribution system that automatically establishes proper phase relationships between clock signals without requiring external calibration. The clock gating circuits inherently provide the necessary phase alignment through their design, eliminating the need for complex calibration procedures and reducing overall system complexity.
Solution Approach 2:
The patent extracts the clock signal conditioning function into dedicated clock gating circuits that handle phase alignment independently. By separating the clock distribution function from the main DAC conversion path, the system achieves precise time alignment without requiring complex calibration techniques in the main signal path.
3Manufacturing precision
If duty cycle correction blocks are added to align clock phases, then phase alignment is improved, but device area and power consumption increase
Solution Approach 1:
The patent combines the phase alignment and clock gating functions into a single integrated circuit block. By merging the duty cycle correction and clock distribution functions into unified clock gating circuits, the system achieves proper phase alignment without requiring separate correction blocks, thereby reducing overall device area.
Data Source
AI summary
In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.