Clock Driver Device Power Consumption Reduction

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Solution Overview

Problem

Conventional semiconductor memory apparatuses experience increased power consumption due to continuous activation of clock drivers, even in power-down modes, leading to unnecessary current consumption along transmission lines.

Innovation Solution

A clock driver device with a driving controller that generates a clock output enable signal in response to an internal read pulse signal and disables it upon a data output enable signal, allowing the clock driver to operate only during actual data output operations, reducing power consumption by preventing unnecessary current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the clock driver is continuously activated to ensure data output capability, then the data output function is maintained, but power consumption increases due to unnecessary current flow along the transmission line

Engineering Contradiction:
Improvedata output functionVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The clock driver's operation state is made dynamic rather than static. The driving controller continuously monitors the data output enable signal and adjusts the clock driver's activation state accordingly, transitioning from continuous operation to on-demand operation based on actual data output requirements

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

A feedback mechanism is implemented where the data output enable signal is fed back to the driving controller, which then controls the clock driver's operation. This closed-loop control ensures the clock driver operates only when data output is actually needed, eliminating unnecessary power consumption while maintaining reliability

Inventive Principle:
Principle #23Feedback

2Use of energy by moving object

If the clock driver operates only during data output operations, then power consumption is reduced, but the risk of data output failure increases if the clock driver is not activated in time

Engineering Contradiction:
Improvepower consumptionVSAvoiddata output reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The driving controller is designed to activate the clock driver in advance based on the data output enable signal timing. By preparing the clock driver activation before the actual data output operation begins, the system ensures the clock driver is ready when needed without continuous operation, balancing power savings with reliability

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If the active command signal is commonly input to multiple semiconductor memory apparatuses, then coordination between devices is improved, but power consumption increases when devices are in power-down mode

Engineering Contradiction:
Improvedevice coordinationVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The clock driver activation is made local to each semiconductor memory apparatus's actual operational state. Instead of uniformly responding to the active command signal, each apparatus's clock driver independently adjusts its operation based on its own power-down status and data output enable signal, allowing coordinated operation when needed while saving power when not required

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS7916562B2Clock driver device and semiconductor memory apparatus having the same
Publication Date: 2011.03.29 SK HYNIX INC
  • US7916562B2 patent drawing
  • US7916562B2 patent drawing
  • US7916562B2 patent drawing

AI summary

A clock driver device includes a driving controller configured to generate a clock output enable signal enabled in response to an internal read pulse signal and disabled in response to a data output enable signal and an internal clock signal, and a clock driver configured to generate a driving clock signal by driving the internal clock signal in response to the clock output enable signal and a power-down signal.