Resonant Clock Drivers With Isolated Energy Recovery Paths
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Solution Overview
Problem
On-chip clocking circuits experience significant power consumption and heating due to repetitive energization and de-energization, limiting their performance, and existing methods like dynamic voltage and frequency scaling (DVFS) either waste energy or are not compatible with high-speed operations.
Innovation Solution
A resonant clock distribution network with energy-saving components that resonate with parasitic capacitance, allowing for energy recovery and reuse during voltage transitions without disrupting critical signal paths, enabling reduced power consumption and heating across a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If resonant strategies are used to reduce clock system heating, then energy consumption is reduced, but the resonant frequency may interfere with output clock signal paths and increase skew
Solution Approach 1:
An intermediary component (resonant circuit) is introduced between the clock driver and the load capacitance to recover energy. The resonant circuit is coupled through a transformer or isolation mechanism that allows energy recovery without directly interfering with the critical clock signal path, thus mediating between energy efficiency goals and signal integrity requirements
Solution Approach 2:
The clocking system is segmented into separate functional blocks: the critical clock signal path remains isolated and undisturbed, while the energy recovery function is implemented in a separate resonant circuit that couples to the load capacitance through controlled interfaces. This segmentation allows independent optimization of signal integrity and energy efficiency
2Use of energy by stationary object
If dynamic voltage and frequency scaling (DVFS) is used to save average energy, then power consumption is reduced over extended use, but energy is wasted every time an output transitions from one to zero states
Solution Approach 1:
The invention recovers energy that would otherwise be discarded during voltage transitions. The resonant circuit captures the energy released when the load capacitance discharges from one state to another, storing it temporarily and returning it to the power supply or reuse it, thereby preventing the energy waste that occurs in conventional DVFS approaches during transitions
3Temperature
If adiabatic charging and discharging is used to reduce heating, then energy efficiency is improved, but the method cannot be used concurrently at GHz speeds
Solution Approach 1:
The invention employs resonant oscillation (analogous to mechanical vibration principles) at frequencies significantly higher than the clock frequency to enable rapid energy recovery cycles. The resonant circuit oscillates at its natural frequency, allowing energy to be recovered and reused many times within a single clock period, thus supporting GHz-speed operation while maintaining the heating reduction benefits of adiabatic techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption by reusing energy during transitions, minimizing heating, and is compatible with dynamic voltage and frequency scaling, achieving significant power savings in high-speed operations without the limitations of traditional methods.
Implementation Method 1
The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance
Implementation Method 2
The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency
Data Source
AI summary
Described herein are reduced-power electronic circuits with wide-band energy recovery using non-interfering topologies. A resonant clock distribution network comprises a plurality of resonant clock drivers that receive at least one of a plurality of reference clock signals. An energy saving component is coupled with the plurality of resonant clock drivers. The energy saving component provides for lower energy consumption by resonating with unwanted parasitic capacitance of a load capacitance. The energy saving component and the load capacitance (LC) form a series resonant frequency that is significantly greater than a clock frequency of the plurality of resonant clock drivers, so that output clock signal paths are not interfered with and so that effects on skew are minimized.