Clock Dropout Protection Circuit for Seamless Sync Switching

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Solution Overview

Problem

Existing electrical charging systems face challenges in maintaining a continuous clock signal during dropout conditions, leading to potential stalling or damage in devices relying on power converters.

Innovation Solution

A dropout protection circuit that seamlessly switches between an external clock signal and an internal clock signal, using a synchronization control circuit to determine signal validity and a simpler approach than phase-locked loops, reducing area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If phase-locked loops are used to maintain clock signal during dropout conditions, then clock signal continuity is improved, but device complexity and power consumption increase

Engineering Contradiction:
Improveclock signal continuityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts only the essential functionality needed for clock continuity - a simple switch between external and internal clock sources - while removing the complex phase-locked loop circuitry. This is achieved through a dropout protection circuit that directly monitors clock presence and switches sources without requiring phase detection or frequency locking mechanisms.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent employs a simpler, less expensive clock switching mechanism that sacrifices the sophisticated error correction and phase alignment capabilities of PLLs in favor of a more straightforward source switching approach. The internal clock serves as a temporary replacement during dropout conditions, accepting that perfect synchronization may not be maintained throughout the transition.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Reliability

If phase-locked loops are used to maintain clock signal during dropout conditions, then clock signal continuity is improved, but power consumption increases

Engineering Contradiction:
Improveclock signal continuityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the power-intensive components of phase-locked loops - specifically the phase detectors, voltage-controlled oscillators, and loop filters - and replaces them with a simple clock presence detector and source switch. This extraction of essential functionality dramatically reduces power consumption while maintaining the core capability of ensuring clock continuity during dropout events.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If dropout protection circuit is used to switch between clock signals, then device complexity is reduced, but clock signal transition smoothness may worsen

Engineering Contradiction:
Improvecircuit complexityVSAvoidclock signal stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The patent prepares for clock transitions by continuously monitoring the presence and validity of the external clock signal in advance. The dropout protection circuit detects clock abnormalities before they cause system failure, allowing proactive switching to the internal clock source. This preliminary detection and preparation minimizes disruption to system operation despite the simplicity of the switching mechanism.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250330180A1Clock SYNC input dropout protection
Publication Date: 2025.10.23 TEXAS INSTRUMENTS INC
  • US20250330180A1 patent drawing
  • US20250330180A1 patent drawing
  • US20250330180A1 patent drawing

AI summary

In a described example, a circuit includes a pulse generator having an input and an output and an oscillator having an output. The circuit also includes a logic circuit having a first input, a second input, and an output, the first input of the logic circuit coupled to the output of the pulse generator, and the second input of the logic circuit coupled to the output of the pulse generator. Additionally, the circuit includes an output circuit having a first input, a second input, a third input and an output, the second input of the output circuit coupled to the output of the logic circuit.