Clock Generation Circuit With Dual Thresholds to Prevent False Clocks
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Solution Overview
Problem
Existing clock generation circuits in imaging devices, such as those using Schmitt trigger circuits, experience high through-currents and generate false clocks due to meta-stable states, leading to erroneous processing and increased power consumption.
Innovation Solution
A clock generation circuit comprising first and second logic circuits with different threshold values and a switch circuit that outputs a clock based on the logic states of these signals, reducing through-currents by only changing the output clock when both signals reach the same state, thereby minimizing false clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Schmitt trigger circuit is used for clock generation, then the circuit can provide hysteresis and noise immunity, but it generates high through-currents and false clocks due to meta-stable states
Solution Approach 1:
The Schmitt trigger circuit is divided into two separate inverters with different threshold values instead of a single integrated circuit. This segmentation allows independent optimization of each inverter's threshold, reducing the overall through-current while maintaining noise immunity through the threshold difference mechanism.
Solution Approach 2:
The invention changes the threshold parameter of the inverters by adjusting transistor width ratios. The first inverter has a lower threshold (achieved by specific transistor width ratios) and the second has a higher threshold, allowing the circuit to maintain hysteresis functionality while reducing through-current consumption compared to conventional Schmitt trigger designs.
2Speed
If the output clock changes frequently to respond to input variations, then the circuit responds quickly to input changes, but it increases power consumption and causes erroneous processing
Solution Approach 1:
The invention implements feedback through the sequential connection of two inverters where the output of the first feeds into the second. This feedback mechanism ensures that the output clock only changes when both inverters have completed their threshold crossings, filtering out spurious transitions while maintaining rapid response to valid input changes, thus reducing unnecessary power consumption.
Solution Approach 2:
The first inverter performs preliminary threshold comparison before the second inverter finalizes the output transition. This preliminary action ensures that only significant input changes trigger output clock transitions, preventing premature or erroneous clock changes that would increase power consumption and cause processing errors.
Data Source
AI summary
A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.