Clock Duty Cycle Adjuster With Monitor Offset Calibration
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a mode register allows for precise monitoring and adjustment of internal clock duty cycles, using a range of adjustment steps and multiple step sizes to compensate for systemic duty cycle errors, ensuring accurate timing and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a duty cycle adjuster circuit is implemented to correct duty cycle distortion, then clock timing accuracy is improved, but device complexity increases
Solution Approach 1:
The duty cycle monitor and duty cycle adjuster are integrated into a single unified circuit block within the memory device. The monitor portion detects duty cycle distortion in the internal clock signal, and the adjuster portion automatically compensates for the distortion, merging monitoring and correction functions into one compact unit that reduces overall system complexity while maintaining high duty cycle accuracy.
Solution Approach 2:
The duty cycle adjuster circuit operates autonomously by using its own internal clock signal as the input to be monitored and corrected. The monitor portion continuously self-tests the duty cycle of the internal clock, and the adjuster portion automatically adjusts the signal to compensate for any distortion, enabling the circuit to self-correct without requiring external control or additional complex control logic.
2Manufacturing precision
If multiple adjustment steps and step sizes are implemented in the duty cycle adjuster, then duty cycle correction precision is improved, but ease of operation deteriorates
Solution Approach 1:
The duty cycle adjuster implements dynamic adjustment with multiple step sizes that can be selectively applied. The circuit can perform coarse adjustments using larger step sizes to quickly bring the duty cycle close to the target value, then switch to finer step sizes for precise final tuning. This dynamic multi-resolution approach achieves high adjustment precision while maintaining operational simplicity through automated control.
Solution Approach 2:
The duty cycle monitor provides continuous feedback to the adjuster circuit, enabling automatic closed-loop control. The monitor detects the actual duty cycle of the internal clock signal and feeds this information back to the adjuster, which automatically selects and applies appropriate adjustment steps to correct the distortion. This feedback mechanism eliminates the need for manual trial-and-error adjustment, simplifying operation while achieving precise duty cycle correction.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.