Clock Duty Cycle Adjuster Calibration Using Monitor Feedback
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature in semiconductor devices, utilizing mode registers to adjust internal clock duty cycles and monitor for distortion, allows for precise timing adjustments to compensate for systemic duty cycle errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If duty cycle adjuster circuits are used to adjust internal clock duty cycles, then timing accuracy of internal clocks is improved, but the adjuster circuits require accurate settings that are difficult to achieve
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors its own clock duty cycle performance and automatically adjusts the duty cycle adjuster settings based on measured deviations. The memory controller sends test commands and reads back duty cycle information, allowing the memory device to self-correct timing errors without requiring manual calibration or complex external adjustment circuits.
Solution Approach 2:
The memory device performs self-diagnosis and self-adjustment of clock duty cycle parameters. By incorporating duty cycle monitoring and automatic adjustment capabilities within the memory device itself, the system eliminates the need for complex external calibration equipment or manual setting procedures, allowing the device to service its own timing accuracy requirements.
2Reliability
If duty cycle adjuster circuits are implemented, then duty cycle distortion is reduced, but the device requires additional monitoring and adjustment mechanisms
Solution Approach 1:
The patent combines the duty cycle monitoring, measurement, and adjustment functions into an integrated system within the memory device. The duty cycle adjuster circuit is merged with the existing clock generation and control logic, allowing monitoring and adjustment to be performed using existing infrastructure rather than adding separate complex monitoring and adjustment subsystems.
Solution Approach 2:
The duty cycle adjuster circuit is designed to work with multiple clock signals and various memory operations simultaneously. The same adjustment mechanism serves multiple functions: correcting duty cycle distortion during read operations, write operations, and different memory modes, thereby reducing the need for separate specialized circuits for each operation type.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.