Clock Duty Cycle Adjuster Calibration Using Monitor Offset Feedback
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Solution Overview
Problem
Semiconductor memories face issues with duty cycle distortion in clock timing, leading to erroneous operations due to deviations from the ideal 50% duty cycle, which existing duty cycle adjuster circuits may not adequately address without accurate settings.
Innovation Solution
The implementation of a duty cycle monitor (DCM) and duty cycle adjuster (DCA) feature within a semiconductor device's mode register, allowing for precise adjustment of internal clock duty cycles through programmable opcode settings, which monitor and correct duty cycle distortion in real-time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If duty cycle adjuster circuits are used to adjust internal clock duty cycle, then duty cycle distortion is reduced, but the adjustment is insufficient unless the adjuster circuits are set accurately
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors its own clock duty cycle performance and automatically adjusts the duty cycle adjuster settings based on measured deviations. The memory device sends duty cycle adjustment requests to the memory controller, which then modifies the settings of the duty cycle adjuster circuits in subsequent operations, creating a closed-loop system that continuously improves duty cycle accuracy without requiring precise manual calibration.
2Reliability
If multiple duty cycle settings are tested to find optimal adjustment, then duty cycle accuracy is improved, but operational time increases
Solution Approach 1:
The patent performs duty cycle testing and measurement during idle periods or between normal memory operations, rather than requiring dedicated calibration time. The system accumulates duty cycle measurements and determines optimal settings during transitions or unused time slots, thereby improving duty cycle accuracy without significantly impacting operational throughput or requiring separate calibration phases.
Data Source
AI summary
Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.