Clock Signal Duty Code Normalization for Stable Duty Cycle
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Solution Overview
Problem
Frequency synthesizers struggle to maintain a constant duty cycle for clock signals as the clock frequency changes, which affects the reliability and efficiency of clock signal generation in digital systems.
Innovation Solution
A method and apparatus that normalize a duty code to a period code, using a normalized duty code generation circuit to control the rising and falling timings of clock signals, ensuring a constant duty cycle even when the clock frequency changes, by shifting and multiplying code bits to generate a normalized duty code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock frequency is changed in a frequency synthesizer, then the clock frequency is adjusted to meet different system requirements, but the duty cycle becomes variable which affects system reliability and efficiency
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing the relationship between frequency division ratios and duty cycle normalization factors in lookup tables before operation. When frequency changes occur, the system retrieves pre-computed normalization values rather than calculating them in real-time, ensuring the duty cycle remains constant despite frequency adjustments. This pre-computation approach resolves the contradiction by preparing compensation data in advance that maintains duty cycle stability during frequency transitions.
Solution Approach 2:
The patent implements feedback by continuously monitoring the actual duty cycle of the generated clock signal and comparing it with the target duty cycle value. Based on this comparison, the system adjusts the normalization factor applied to the duty cycle control signal, creating a closed-loop control mechanism. This feedback loop ensures that even when frequency changes cause duty cycle deviations, the system automatically compensates to maintain the desired duty cycle, thereby resolving the contradiction between frequency adaptability and duty cycle stability.
2Productivity
If traditional frequency synthesizer methods are used to generate clock signals, then frequency adjustment is achieved through simple division, but the duty cycle cannot be maintained constant due to the interaction between frequency division and duty cycle control
Solution Approach 1:
The patent introduces a duty cycle normalization circuit as an intermediary component between the frequency synthesis stage and the output stage. This intermediary circuit receives both the frequency control signal and the duty cycle control signal, processes them through normalization logic that accounts for the frequency division ratio, and produces a corrected duty cycle control signal. This intermediary mechanism resolves the contradiction by decoupling the frequency adjustment function from the duty cycle control function, allowing fast frequency synthesis while maintaining precise duty cycle accuracy through the normalization intermediary.
Data Source
AI summary
A clock signal generating method includes receiving a duty code that represents a duty of a clock signal, and a period code that represents a period of a clock signal, and normalizing the duty code to the period code to output a normalized duty code. The clock signal generating method further includes controlling a rising timing of a clock signal in response to the period code, and controlling a falling timing of the clock signal in response to the normalized duty code to generate a timing-controlled clock signal.