Clock Duty Cycle Calibration Circuit for High-Speed Memory BIST
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Solution Overview
Problem
Current semiconductor memory testing equipment struggles to accurately assess high-speed memory devices due to limited frequency capabilities and difficulty in maintaining stable duty cycles, leading to inaccurate test results and high dependence on Automatic Test Equipment (ATE).
Innovation Solution
A clock generation circuit that includes an oscillation circuit generating differential high-frequency oscillation signals, a comparison unit to monitor and adjust duty cycles, and a logical unit to control the oscillation circuit, ensuring duty cycles fall within a preset range, thereby reducing reliance on external test equipment and improving test accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current mainstream test equipment is used to provide input signals for memory testing, then the test equipment can operate at relatively low frequencies (about 200 MHz), but it cannot accurately assess high-speed memory devices operating at maximum working frequency and cannot ensure stable duty cycle
Solution Approach 1:
The memory device performs self-testing by generating its own high-frequency clock signals internally through an oscillation circuit, eliminating dependence on external test equipment. The built-in clock generation circuit includes an oscillation circuit, comparison unit, and logical unit that work together to generate and calibrate clock signals at the memory's maximum operating frequency, enabling accurate self-assessment without external equipment limitations
Solution Approach 2:
The patent extracts the clock generation and calibration functions from external test equipment and implements them within the memory device itself. By removing the dependency on external ATE for clock signal generation, the memory can operate at its full speed potential and perform accurate self-testing, effectively taking out the limiting factor from the testing system
2Productivity
If external test equipment is used for memory testing, then testing can be performed, but high dependence on Automatic Test Equipment (ATE) increases test costs
Solution Approach 1:
The memory device is equipped with built-in DCA and DCM circuits that enable it to perform its own testing and calibration. The device generates internal clock signals, monitors duty cycle accuracy, and adjusts parameters autonomously, completely eliminating the need for expensive external ATE and reducing test costs while maintaining full testing capability
3Ease of operation
If the duty cycle of clock signals is not calibrated, then the clock generation circuit can operate, but duty cycle distortion occurs causing wrong operation
Solution Approach 1:
The patent implements a feedback mechanism where the comparison unit continuously monitors the duty cycle of clock signals generated by the oscillation circuit. When duty cycle distortion is detected, the logical unit receives the comparison result and adjusts the oscillation circuit parameters to correct the distortion, ensuring the duty cycle remains within the preset range and preventing wrong operation
Solution Approach 2:
The calibration function is performed preliminarily before the memory device is delivered to ensure duty cycle accuracy. The DCA circuit pre-adjusts the clock signals to meet specification requirements, and the DCM circuit verifies the calibration results, preventing reliability issues before they occur in field operation
Data Source
AI summary
A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.