Clock Duty-Cycle Correction with Digital Feedback in Burst Mode
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Solution Overview
Problem
Conventional duty-cycle correction circuits face challenges in maintaining a 50% duty cycle in burst mode applications, leading to increased power consumption and long settling times due to analog loop requirements.
Innovation Solution
A digital domain feedback path is implemented in the duty cycle correction circuit, allowing for reduced settling time and power consumption by storing a delay generation value and using programmable delays to adjust the clock signal's duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog loop duty cycle correction is used, then duty cycle accuracy can be maintained, but settling time increases and power consumption increases
Solution Approach 1:
The patent replaces the analog loop correction mechanism with a digital domain feedback path. The duty cycle correction is achieved through digital signal processing and control logic rather than analog continuous adjustment, which eliminates the need for long settling periods characteristic of analog loops while maintaining correction accuracy.
Solution Approach 2:
The patent implements periodic measurement of the duty cycle using a duty cycle detector that samples the clock signal at regular intervals. This periodic digital measurement and correction approach allows the system to maintain accuracy without requiring continuous analog adjustment, thereby reducing settling time.
2Measurement precision
If conventional analog loop duty cycle correction is used, then duty cycle accuracy can be maintained, but power consumption increases
Solution Approach 1:
The patent substitutes the power-hungry analog loop correction circuitry with a digital domain implementation. The digital feedback path uses programmable delay elements and digital logic to achieve duty cycle correction, which consumes significantly less power than continuous analog adjustment mechanisms while preserving correction precision.
Solution Approach 2:
The duty cycle detector continuously monitors the clock signal and provides feedback to the correction logic, enabling the system to self-correct duty cycle errors without requiring high-power external intervention. The digital nature of this self-monitoring and self-correction process minimizes power consumption compared to analog approaches.
3Loss of time
If programmable delay elements are used for duty cycle correction, then settling time is reduced, but device complexity increases
Solution Approach 1:
The patent employs programmable delay elements that serve multiple functions: they are used both for duty cycle correction and for generating test patterns. This multi-functionality reduces the need for separate dedicated circuits, thereby managing complexity while achieving fast settling through digital programmable delays.
Solution Approach 2:
The patent uses digitally programmable delay elements where the delay parameter can be dynamically adjusted based on measured duty cycle errors. This parameter control approach allows precise correction with relatively simple circuitry compared to analog continuous adjustment, achieving fast settling without excessive complexity.
Data Source
AI summary
A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.