Duty Cycle Calibration Circuit for Reference-Independent Measurement

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Solution Overview

Problem

Existing duty cycle calibration methods are prone to inaccurate measurements due to external influences on reference clock signals, leading to low precision in duty cycle calibration.

Innovation Solution

A duty cycle calibration circuit comprising a counting unit, a control unit, and a duty cycle adjustment unit, where the counting unit acquires counting pulses with a higher frequency clock signal to determine the actual duty cycle, and the control unit adjusts the duty cycle until it reaches a target value.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a reference clock signal is used to measure the duty cycle of a calibration clock signal, then the measurement process is simple, but the measurement accuracy deteriorates due to external influences on the reference clock signal

Engineering Contradiction:
Improveduty cycle measurement accuracyVSAvoidexternal influences on reference clock signal
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a counting clock signal as an intermediary measurement standard. Instead of directly comparing the calibration clock signal with a vulnerable reference clock signal, the system uses a high-frequency counting clock signal to generate counting pulses that indirectly measure the duty cycle. This intermediary approach isolates the measurement process from external influences affecting the reference clock signal, thereby improving measurement accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the measurement parameter from direct time duration comparison to counting pulse quantity measurement. By using a high-frequency counting clock signal, the system converts the duty cycle measurement into a digital counting process, where the number of counting pulses during high and low levels of the calibration clock signal provides a more accurate and stable measurement that is less susceptible to external disturbances.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If the counting clock signal frequency is increased to improve measurement resolution, then the duty cycle measurement precision improves, but the device complexity increases

Engineering Contradiction:
Improveduty cycle measurement precisionVSAvoidcounting unit and control circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a self-calibrating control mechanism where the control unit automatically adjusts the duty cycle of the calibration clock signal based on the comparison between measured and target duty cycles. The system uses itself as the calibration object, eliminating the need for external calibration equipment and reducing overall system complexity despite the high-frequency counting mechanism.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent employs a feedback control loop where the measured duty cycle is continuously compared with the target duty cycle, and the difference is used to generate control signals that adjust the calibration clock signal's duty cycle. This closed-loop feedback mechanism automates the calibration process, reducing manual intervention and simplifying the user interface despite the underlying circuit complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4503437A1Duty cycle calibration circuit and method, chip, and electronic device
Publication Date: 2025.02.05 AMLOGIC (SHANGHAI) CO LTD
  • EP4503437A1 patent drawingFigure 1~2
  • EP4503437A1 patent drawingFigure 3
  • EP4503437A1 patent drawingFigure 4~6

AI summary

Provided are a duty cycle calibration circuit and method, a chip, and an electronic device. In the duty cycle calibration circuit, through a counting clock signal having a higher clock signal frequency than a calibration clock signal, a counting unit is configured to acquire a number of counting pulses generated in a high-level state and a low-level state of the calibration clock signal within a preset counting period, so as to obtain an actual duty cycle of the calibration clock signal. Compared with a method of acquiring a duty cycle of a calibration clock signal by comparing the calibration clock signal with a reference clock signal, inaccurate measurement of the duty cycle of the calibration clock signal after the reference clock signal is affected can be overcome. Therefore, accuracy of measurement of the duty cycle can be improved, and precision of calibration of the duty cycle can be improved accordingly.