Clock Synthesizer Duty Cycle Correction for Fast 50% Clocks
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Solution Overview
Problem
Existing methods for correcting duty cycle errors in clock signals are time-consuming and require complex circuits with high power consumption, often failing to achieve rapid correction.
Innovation Solution
A clock synthesizer with a Duty Cycle Corrector (DCC) circuit that adjusts the duty cycle of clock signals to 50% using a Phase Locked Loop (PLL), buffer, and DCC circuit, incorporating a Duty Cycle Alterer (DCA) with invertors, DC samplers, error amplifier, loop filter, and adaptive current sources to minimize DC voltage differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If iterative adjustment of delays is used to correct duty cycle error, then duty cycle accuracy is improved, but correction time increases significantly
Solution Approach 1:
The patent pre-calculates and stores delay values in a lookup table that map directly to required duty cycle corrections. When duty cycle error is detected, the system immediately retrieves the pre-computed correction value from the table without iterative adjustment, achieving both high accuracy and fast correction.
Solution Approach 2:
The patent replaces the mechanical iterative adjustment process with a direct computational lookup mechanism. Instead of physically adjusting delay circuits through multiple cycles, the system uses a mathematical model to calculate the exact correction needed and applies it immediately through memory access and signal processing.
2Measurement precision
If iterative duty cycle correction is implemented, then duty cycle precision is improved, but circuit complexity increases
Solution Approach 1:
The patent replaces complex iterative control circuits with a simpler lookup table and direct calculation system. The lookup table stores pre-computed delay values, and a simple comparator and memory access mechanism retrieve the appropriate correction, eliminating the need for complex iterative adjustment logic.
Solution Approach 2:
The patent uses a lookup table that contains pre-stored copies of optimal delay values for various duty cycle conditions. Instead of computing corrections through complex circuits, the system copies the appropriate pre-calculated value from the table, simplifying the circuit while maintaining precision.
3Measurement precision
If iterative duty cycle correction is used, then duty cycle accuracy is improved, but power consumption increases
Solution Approach 1:
The patent pre-computes and stores all necessary duty cycle correction values in a lookup table during manufacturing or initialization. During operation, the system only needs to retrieve pre-computed values and apply them, avoiding the continuous power-intensive iterative calculations and adjustments of traditional methods.
Solution Approach 2:
The patent substitutes power-intensive iterative adjustment circuits with a low-power lookup and retrieval mechanism. The system uses simple memory access and signal routing instead of continuous active adjustment, dramatically reducing power consumption while maintaining accuracy.
Data Source
AI summary
A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.