Adaptive Clock Duty-Cycle Control for Aging-Induced Distortion
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Solution Overview
Problem
Asymmetric aging in clock distribution networks causes duty-cycle distortion in clock signals, leading to timing issues in circuits due to uneven delays in signal paths, which existing technologies fail to adequately address.
Innovation Solution
A timing measurement circuit comprising a launch circuit, capture circuit, and time-to-digital converter (TDC) is employed to measure timing parameters of the clock signal, allowing for precise compensation of duty-cycle distortion by adjusting the clock signal's duty cycle through an adaptive duty-cycle controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock distribution network is used to distribute clock signals, then clock signals can be delivered to multiple circuits, but asymmetric aging in signal paths causes duty-cycle distortion and timing violations
Solution Approach 1:
The patent applies preliminary action by measuring the timing characteristics of clock signal paths in advance using launch circuits and capture circuits. The measured data is stored and used to compensate for duty-cycle distortion before it affects timing operations, allowing the system to proactively correct for aging effects rather than reacting to timing violations after they occur.
Solution Approach 2:
The patent implements feedback by continuously measuring the actual timing characteristics of clock signal paths using timing measurement circuits and TDCs. The measured duty-cycle distortion information is fed back to control circuits that adjust delay elements to compensate for the distortion, creating a closed-loop system that maintains timing accuracy despite asymmetric aging in the clock distribution network.
2Measurement precision
If timing measurement circuits are added to measure clock signal parameters, then duty-cycle distortion can be compensated, but device complexity increases
Solution Approach 1:
The patent applies universality by designing timing measurement circuits that can measure multiple timing parameters (duty cycle, skew, delay) using the same basic infrastructure of launch circuits, capture circuits, and TDCs. This multi-functional approach allows a single measurement system to handle various timing characterization needs without requiring separate dedicated circuits for each measurement type, thereby reducing overall complexity.
Solution Approach 2:
The patent implements nesting by integrating the timing measurement functionality within the existing clock distribution network infrastructure. The launch circuits and capture circuits are embedded within or alongside the clock distribution elements, and the TDCs are integrated into the same chip or module. This nested arrangement allows timing measurements to be performed using the existing signal paths and components, minimizing the addition of external complex circuitry.
Data Source
AI summary
A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.