Clock Duty Cycle Calibration Circuit for Serial Timing Jitter
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Solution Overview
Problem
High-speed serial communication over wired interconnections experiences timing jitter due to duty cycle distortion in the clock signal, leading to timing errors in transmitted symbols, which existing correction techniques fail to adequately address without proper measurement and calibration.
Innovation Solution
A duty cycle correction technique involving a transmitter-side calibration circuit that measures duty cycle distortion by averaging or low-pass filtering input and shifted calibration patterns, using a comparator or ADC to correct the duty cycle to 50% without requiring receiver involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle measurement is performed using high-speed clock edges, then timing precision is improved, but the system becomes sensitive to supply and noise effects
Solution Approach 1:
The patent applies preliminary action by performing duty cycle calibration during a calibration phase before normal data transmission. The calibration pattern is transmitted at a lower data rate during this preliminary phase, allowing accurate duty cycle measurement without the harmful effects of high-speed operation. Once calibrated, the duty cycle correction parameters are stored and applied during normal high-speed operation without continuous calibration.
2Measurement precision
If duty cycle correction is implemented at the receiver side, then measurement accuracy is improved, but device complexity and communication overhead increase
Solution Approach 1:
The patent inverts the conventional approach by implementing duty cycle measurement and correction at the transmitter side instead of the receiver side. The transmitter measures its own clock duty cycle using a calibration pattern and applies correction locally. This eliminates the need for complex receiver measurement features and reduces communication overhead, as the correction is applied before data transmission without requiring feedback from the receiver.
3Speed
If high-speed data transmission is used, then communication speed is improved, but timing jitter increases due to duty cycle distortion
Solution Approach 1:
The patent applies preliminary action by performing duty cycle calibration before high-speed data transmission. During the calibration phase, the transmitter measures the duty cycle of its clock signal using a calibration pattern transmitted at a lower rate. Based on this measurement, correction parameters are calculated and applied to compensate for duty cycle distortion. This preliminary calibration ensures that subsequent high-speed transmission maintains accurate timing performance without being affected by duty cycle distortion.
Data Source
AI summary
In embodiments, a clock signal calibration circuit for communication transmitters includes a multiplexer that creates a combined output pattern from input data patterns in reaction to the clock signal's edges. It uses a calibration data pattern generator, which supplies two sequential patterns—the second being a shifted copy of the first—to the multiplexer. An averaging circuit then generates two averaged signals corresponding to these patterns. Duty cycle control circuitry corrects clock signal imbalances if these averaged signals are unequal, thus adjusting the duty cycle distortion to achieve an ideal 50% duty cycle.