Clock Tracking Circuit Duty Cycle Matching for Low Jitter
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Solution Overview
Problem
Existing clock tracking circuits face issues with duty cycle mismatch between reference and output clocks, leading to increased jitter and spurs, as separate corrections for duty-cycle distortion in each clock signal result in cumulative errors.
Innovation Solution
A clock tracking circuit with an integrated duty cycle matching mechanism that synchronizes and adjusts the duty cycles of both reference and output clocks using a hybrid phase locked loop, incorporating error detection, controlled oscillators, and duty cycle matching circuits to reduce mismatch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate duty cycle corrections are applied to reference clock and output clock independently, then each clock's duty cycle distortion is corrected, but cumulative errors increase leading to greater duty cycle mismatch
Solution Approach 1:
The patent merges the duty cycle correction operations for the reference clock and output clock into a single integrated correction mechanism. Instead of independently correcting each clock separately, the system combines their duty cycle adjustments into one coordinated process, eliminating the cumulative errors that arise from separate corrections and reducing the overall duty cycle mismatch between the two clocks.
2Object-affected harmful factors
If duty cycle mismatch between reference and output clocks is not corrected, then circuit complexity remains low, but jitter and spurs increase
Solution Approach 1:
The patent introduces an intermediary duty cycle matching circuit that acts as a mediator between the reference clock and output clock. This intermediary component specifically addresses the duty cycle mismatch without requiring complete redesign of the entire clock tracking system, thereby reducing jitter and spurs while adding only the necessary complexity to achieve the matching function.
3Reliability
If integrated duty cycle matching is implemented, then duty cycle mismatch and jitter are reduced, but circuit complexity increases
Solution Approach 1:
The patent implements a universal duty cycle matching mechanism that serves multiple functions simultaneously: it corrects duty cycle distortion in both the reference and output clocks, matches their duty cycles to each other, and reduces jitter and spurs. By creating a multi-functional circuit component, the system achieves improved clock tracking stability without proportionally increasing overall circuit complexity, as a single integrated block performs what would otherwise require multiple separate correction mechanisms.
Data Source
AI summary
One or more examples relate to a method. The method may include: setting, at least partially based on an indication of mismatch between duty cycles of a first clock and a second clock generated to track the first clock, a duty cycle of a third clock; and providing the third clock having set duty cycle to an error detector of the clock tracking circuit in place of one of the first clock or the second clock.