Clock Duty Cycle Calibration Circuit for High-Speed Memory Testing
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Solution Overview
Problem
Current test equipment for high-speed semiconductor memory, such as LPDDR4, LPDDR5, and LPDDR6, struggles to accurately test high-speed input ports due to limited frequency capabilities and difficulty in maintaining stable duty cycles, leading to inaccurate test results and high dependence on Automatic Test Equipment (ATE).
Innovation Solution
A clock generation circuit within the memory that generates high-frequency differential oscillation signals, allowing for Built-In Self Test (BIST) functionality, Duty Cycle Adjustment (DCA), and Duty Cycle Monitoring (DCM), which includes an oscillation circuit, comparison unit, and logical unit to adjust and stabilize the duty cycles of the clock signals to a preset range, reducing reliance on external test equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external test equipment is used to provide input signals for memory testing, then testing capability is provided, but test accuracy deteriorates due to limited frequency capability and inability to maintain stable duty cycles
Solution Approach 1:
The memory device generates its own high-frequency clock signals through an integrated oscillation circuit, eliminating dependence on external test equipment. The self-test function allows the memory to perform accurate testing at its native high operating frequencies without being limited by external equipment capabilities.
Solution Approach 2:
An integrated clock generation circuit with oscillation circuit, comparison unit, and logical unit serves as an intermediary between the memory and external test equipment. This intermediary generates stable high-frequency clock signals with accurate duty cycles, bridging the gap between limited external equipment and high-speed memory requirements.
2Reliability
If external test equipment operates at low frequency, then equipment complexity is reduced, but test reliability deteriorates due to mismatch with high-speed memory operating frequencies
Solution Approach 1:
The memory device autonomously generates clock signals at its full operating frequency range through the oscillation circuit, enabling reliable testing at high speeds without requiring external equipment to match the memory's operating frequency.
3Manufacturing precision
If duty cycle is not calibrated, then device complexity is reduced, but clock signal quality deteriorates leading to wrong operation
Solution Approach 1:
The comparison unit continuously monitors the duty cycle of generated clock signals and provides feedback to the logical unit, which adjusts the oscillation circuit parameters to maintain accurate duty cycles. This closed-loop feedback ensures high clock signal quality without requiring complex external calibration equipment.
Solution Approach 2:
The oscillation circuit performs preliminary calibration of the clock signal duty cycle before the signals are used for memory operation or testing. This preliminary action ensures that clock signals meet required specifications before being applied to the memory, preventing wrong operation.
Data Source
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AI summary
The embodiments of the application provide a clock generation circuit, a memory and a clock duty cycle calibration method; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range. The embodiments of the application may generate a first oscillation signal and a second oscillation signal with stable duty cycle that may be used for memory testing.