Clock Duty Cycle Correction Circuit Using Segmented Delay Stages
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Solution Overview
Problem
Existing correction circuits face challenges in accurately adjusting the duty cycle of received clocks due to variations in delay unit performance and unintended power supply variations, leading to degraded adjustment accuracy and longer time required for duty cycle correction.
Innovation Solution
A correction circuit comprising a detection unit, a delay unit, and a waveform shaping unit that measures the high-level periods of input clocks, generates delay clocks based on period differences, and adjusts the output clock to achieve a 50% duty cycle by selectively connecting delay units to minimize performance variations and reduce the number of series-connected delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If delay units are series-connected to adjust duty cycle, then duty cycle adjustment range is improved, but delay unit performance variations and power supply fluctuations degrade adjustment accuracy
Solution Approach 1:
The duty cycle adjustment function is divided into two independent parts: a coarse adjustment unit with fewer delay units for large-scale duty cycle correction, and a fine adjustment unit with delay units for precise duty cycle tuning. This segmentation reduces the total number of series-connected delay units, thereby minimizing performance variations and power supply fluctuations while maintaining full adjustment range.
Solution Approach 2:
Different regions of the duty cycle adjustment range are handled by different adjustment units with optimized characteristics. The coarse adjustment unit covers the majority range with robust delay units, while the fine adjustment unit handles the critical near-50% duty cycle region with high-precision delay units, ensuring optimal accuracy where it matters most.
2Measurement precision
If more delay units are series-connected to improve duty cycle adjustment precision, then adjustment accuracy is improved, but time required for duty cycle correction increases
Solution Approach 1:
The two-stage adjustment structure enables rapid coarse correction followed by quick fine-tuning. The coarse adjustment unit quickly brings the duty cycle close to the target value using fewer delay units, reducing the overall correction time, while the fine adjustment unit then makes precise adjustments to achieve the required accuracy.
Solution Approach 2:
The coarse adjustment unit performs preliminary duty cycle correction before the fine adjustment unit takes over. This preliminary action eliminates the need for the fine adjustment unit to handle large deviations, allowing it to converge to the final precise value much faster than if it had to work alone across the full adjustment range.
3Measurement precision
If delay unit performance variations are minimized by reducing series-connected units, then adjustment accuracy is improved, but duty cycle adjustment range may be limited
Solution Approach 1:
The coarse adjustment unit provides the extended adjustment range through multiple delay units configured for large-scale duty cycle changes, while the fine adjustment unit uses fewer high-precision delay units for accurate tuning. Together, they achieve both full adjustment range and high accuracy without requiring all delay units to be series-connected for the entire range.
Solution Approach 2:
The coarse adjustment unit and fine adjustment unit are merged into a unified duty cycle correction system where their outputs are combined. The coarse unit handles the bulk adjustment range requirements, while the fine unit overlays precise corrections, achieving both extended range and high accuracy through their cooperative operation.
Data Source
AI summary
A correction circuit includes a first detection unit, a second detection unit, a delay unit, and a waveform shaping unit. The first detection unit is configured to measure a first period of a high level of a first clock. The second detection unit is configured to measure a second period of a high level of a second clock that is complementary to the first clock. The delay unit is configured to generate a first delay clock and a second delay clock according to a difference between the first period and the second period. The waveform shaping unit is configured to generate a third clock having a logic level which is switched based on an edge of the first delay clock and an edge of the second delay clock.