Internal Clock Duty Control Using Reference Delay Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor integrated circuits face challenges in generating stable internal clocks for semiconductor memory, leading to potential erroneous data latching due to unstable reference clocks, especially during power stabilization and high access speeds.
Innovation Solution
Incorporating a detection circuit and generation circuit with a variable register to delay the detection of reference delay stages until the reference clock is stable, and using time averaging and limit setting to optimize internal clock generation, ensuring accurate phase control and duty ratio adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the reference clock is used immediately after power-on, then the system can start operating faster, but the internal clock becomes unstable causing data latching errors
Solution Approach 1:
The patent implements a reference delay amount detection circuit that performs preliminary detection and stabilization of the reference clock before the internal clock generation begins. The detection circuit measures the reference delay amount through multiple delay stages and stores it in a register, ensuring the reference clock is stable before use. This preliminary action prevents data latching errors while maintaining reasonable startup speed.
2Reliability
If the reference delay amount detection is performed continuously, then the internal clock stability is improved, but the power consumption and processing time increase
Solution Approach 1:
The patent employs periodic action by performing reference delay amount detection at specific intervals rather than continuously. The detection is triggered at predetermined timings such as power-on reset or mode switching events. The detection circuit includes a detection timing generation unit that activates the detection process only when needed, storing results in registers for subsequent internal clock generation without requiring continuous processing.
3Measurement precision
If multiple delay stages are used for accurate reference delay detection, then the measurement precision is improved, but the device complexity increases
Solution Approach 1:
The patent segments the reference delay amount detection into multiple discrete delay stages, where each stage contributes a specific delay amount. The detection circuit includes multiple delay elements connected in series, with each stage representing a portion of the total reference delay. This segmentation allows accurate measurement of the reference delay amount while maintaining modular circuit design, reducing overall complexity compared to a single complex delay element.
Data Source
AI summary
A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.