Delay-Locked Loop Clock Duty-Cycle Correction with Variable Delay
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Solution Overview
Problem
Closed-loop clock circuits, such as phase-locked and delay-locked loops, cannot effectively correct duty-cycle errors in clock signals, which lead to degraded data transmission and increased error rates due to mismatched driver capabilities, signal coupling, and trace capacitance, causing skew and jitter in clock edges.
Innovation Solution
A duty-cycle correction circuit using a variable delay element, combined with successive approximation and linear techniques, adjusts the delay to improve the duty cycle of clock signals received or generated by delay-locked loops, incorporating a fixed delay line and a variable delay line with a latching circuit to construct an output clock signal with an improved duty cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If closed-loop clock circuits are used to generate or receive clock signals, then clock signal cleaning (jitter removal) and retiming are improved, but duty-cycle errors cannot be corrected leading to degraded data transmission
Solution Approach 1:
The clock signal path is segmented into multiple delay elements (first delay element, second delay element, third delay element) that can be independently controlled. This segmentation allows specific portions of the clock signal to be adjusted for duty cycle correction without affecting the overall clock generation function of the closed-loop circuit.
Solution Approach 2:
The invention changes the delay parameter of specific delay elements based on detected duty cycle errors. By dynamically adjusting the delay amount through control signals, the system corrects duty cycle inaccuracies while maintaining the clock signal's frequency and phase characteristics.
2Adaptability or versatility
If driver pull-up and pull-down capabilities are mismatched, then circuit design flexibility is improved, but skew between clock rising and falling edges increases causing duty-cycle errors
Solution Approach 1:
The system uses feedback from the duty cycle detection mechanism to automatically adjust the delay elements. The detected duty cycle error feeds back to control the delay amount, creating a closed-loop system that compensates for skew caused by mismatched driver capabilities without requiring perfect driver matching.
Solution Approach 2:
The delay elements are made dynamic rather than fixed, allowing their delay characteristics to change based on operating conditions. This dynamic adjustment capability enables the system to adapt to driver mismatches and maintain proper clock edge alignment across different operating scenarios.
3Manufacturing precision
If additional circuitry is added to correct duty-cycle errors, then duty cycle accuracy is improved, but device complexity increases
Solution Approach 1:
The delay elements serve multiple functions: they are part of the normal clock signal path for frequency generation, and simultaneously provide duty cycle correction when adjusted. This multi-functionality avoids adding separate dedicated correction circuitry, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The system uses its own existing delay elements and control mechanisms to perform duty cycle correction, rather than requiring entirely separate correction circuitry. The clock circuit's own components are leveraged to fix its own duty cycle errors, reducing the need for additional external correction devices.
Data Source
AI summary
Circuits, methods, and apparatus that provide duty-cycle error correction for clock and other periodic signals. One example provides a duty-cycle correction that can be used to improve the duty cycle of a clock signal that is received by, or generated by, a delay-locked loop. This example receives an input clock signal and uses a variable delay element to construct an improved duty-cycle output clock signal. The duty cycle of the output clock is examined to determine if the delay element is providing excess or insufficient delay. The delay of the delay element is then adjusted. To improve response times, a successive approximation technique is used to determine the most significant bits of a count that adjusts the delay through the delay element. To improve accuracy, a linear technique is used to adjust the least significant bits of the count.