Clock Duty Cycle Correction Using Pulse-Width Difference Detection
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Solution Overview
Problem
Conventional duty cycle correctors face limitations in correcting clock duty cycles, including increased locking time, inaccurate duty ratio measurement due to digital offset, and restricted frequency range, which affects data synchronization in semiconductor memory devices.
Innovation Solution
A duty cycle corrector comprising a duty adjusting unit, a duty detecting unit, and an accumulating unit that measures and corrects the difference between high and low pulse widths of a clock, generating a duty correction code to adjust the clock duty cycle accurately across various frequencies, reducing locking time and enabling precise correction in one cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional duty cycle correctors generate up/down signal by comparing high pulse width with low pulse width and correct the duty ratio little by little, then the duty cycle can be corrected, but the locking time increases
Solution Approach 1:
The patent performs preliminary action by directly calculating the difference value between high pulse width and low pulse width in one cycle, rather than iteratively comparing and correcting. The duty detecting unit measures both pulse widths simultaneously and the subtracting unit computes their difference immediately, eliminating the need for multiple sequential comparison operations and thereby reducing locking time while maintaining measurement accuracy.
2Device complexity
If digital duty cycle correctors use offset-based comparison, then the circuit implementation is simple, but the duty ratio measurement accuracy deteriorates
Solution Approach 1:
The patent extracts and eliminates the offset error source by using a subtracting unit that directly computes the difference between high pulse width and low pulse width measurements. Instead of relying on offset-based comparison that introduces measurement errors, the invention extracts the actual duty cycle distortion by subtracting the measured pulse widths, thereby improving measurement accuracy while keeping the circuit implementation straightforward through basic arithmetic operations.
3Device complexity
If conventional duty cycle correctors use fixed correction methodology, then the circuit design is simple, but the frequency range of correctable clocks is limited
Solution Approach 1:
The patent applies dynamics by making the correction amount adaptive rather than fixed. The duty adjusting unit dynamically adjusts the duty cycle based on the calculated difference value, which can vary with different input clock frequencies and duty cycle distortions. This dynamic adjustment mechanism allows the circuit to handle a wide frequency range and various duty cycle errors without requiring complex reconfiguration, achieving versatility through simple proportional correction.
Data Source
AI summary
A duty cycle corrector includes a duty adjusting unit configured to adjust a duty cycle of an input clock in response to a duty correction code and generate an output clock, a duty detecting unit configured to measure a difference between a high pulse width and a low pulse width of the output clock and output a difference value, and an accumulating unit configured to accumulate the difference value to generate the duty correction code.