Clock Duty Cycle Correction Using Digital Edge Control

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Solution Overview

Problem

Conventional duty cycle correction circuits in semiconductor integrated circuits face challenges in precisely correcting the duty cycle of clock signals due to noise and other factors, leading to inefficiencies and high power consumption.

Innovation Solution

A circuit and method that include a duty ratio digital conversion block, a duty ratio information analyzing block, and a duty ratio control block to generate edge control signals and select delayed clock signals, allowing for precise control of the duty cycle by mixing phases of falling and rising clock signals to achieve a 50:50 duty ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional digital converter types or phase mixer types are used for duty cycle correction, then the circuit can correct the duty ratio of clock signals, but the correction precision is insufficient and power consumption is high

Engineering Contradiction:
Improveduty cycle correction precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The circuit segments the duty cycle correction process into distinct functional blocks: a duty ratio detection unit that measures the actual duty ratio, a signal analyzing unit that processes the detection signals, and an edge control unit that generates correction signals. This segmentation allows each block to be optimized independently, achieving precise correction while controlling power consumption through selective operation of each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit implements a feedback mechanism where the duty ratio detection unit continuously monitors the clock signal's duty ratio, and the edge control unit adjusts the clock signal edges based on the detected deviation from the target 50% duty ratio. This closed-loop feedback ensures precise correction while the system can enter low-power states when correction is not needed.

Inventive Principle:
Principle #23Feedback

2Productivity

If conventional duty cycle correction circuits are used, then the circuit can operate with clock signals, but operational efficiency is lowered due to imprecise duty ratio

Engineering Contradiction:
Improveoperational efficiencyVSAvoidduty ratio precision
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The circuit replaces complex mechanical or analog phase mixing mechanisms with a digital-based edge control approach. The edge control unit generates precise control signals to adjust clock signal edges directly, eliminating the need for bulky phase mixers and enabling more precise duty ratio control that directly improves operational efficiency.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The circuit dynamically changes the timing parameters of clock signal edges based on detected duty ratio deviations. By adjusting the rise and fall edges independently through controlled delay elements, the system achieves precise 50% duty ratio correction, thereby maximizing operational efficiency of the semiconductor integrated circuit.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7576581B2Circuit and method for correcting duty cycle
Publication Date: 2009.08.18 SK HYNIX INC
  • US7576581B2 patent drawing
  • US7576581B2 patent drawing
  • US7576581B2 patent drawing

AI summary

A circuit for correcting a duty cycle includes a duty ratio digital conversion block configured to output duty ratio information of an input clock signal as plural-bit digital signals, a duty ratio information analyzing block configured to analyze the duty ratio information of the input clock signal, generate edge control signals, and select any one of a plurality of delayed clock signals, and a duty ratio control block configured to control duty ratios of a selected delayed clock signal and the input clock signal in response to the edge control signals.