Clock Duty Cycle Correction Using Iterative Error Feedback
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Solution Overview
Problem
Existing semiconductor devices face challenges in accurately correcting clock signal delays and duty cycles, which can lead to data transmission errors due to internal distortions, and current solutions do not adequately address these issues.
Innovation Solution
A clock correction circuit comprising a delay-locked loop, duty cycle correction circuits, and error code generation mechanisms that iteratively refine the clock signal to achieve precise duty cycle correction, using a feedback loop to generate and adjust the clock signal based on error codes, ensuring optimal duty cycle alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop circuit and duty cycle correction circuit are used to compensate for clock signal delays and duty cycles, then data transmission synchronization is improved, but the complexity of the clock correction circuit increases
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detection circuit monitors the corrected clock signal and generates error codes that are fed back to the duty cycle correction circuit. This closed-loop feedback system automatically adjusts the duty cycle without requiring complex external control, thereby improving synchronization reliability while keeping the circuit complexity manageable through self-regulation.
Solution Approach 2:
The clock correction circuit performs self-correction by using its own output signal to generate correction instructions. The duty cycle detection circuit detects the duty cycle of the corrected clock signal and generates error codes that automatically adjust the correction amount, enabling the system to self-regulate and maintain optimal performance without external intervention.
2Measurement precision
If multiple duty cycle correction circuits are used to increase correction accuracy, then duty cycle precision is improved, but the device complexity increases
Solution Approach 1:
The patent employs dynamic adjustment where the duty cycle correction amount is not fixed but varies based on real-time detection results. The error code generation circuit dynamically determines the correction amount based on the detected duty cycle deviation, allowing the system to achieve high precision through adaptive correction rather than through multiple static correction stages.
Solution Approach 2:
The system changes the correction parameter (duty cycle correction amount) based on the error code generated from duty cycle detection. By dynamically adjusting the correction parameter according to the actual duty cycle deviation, the system achieves high correction accuracy without requiring multiple correction circuits, thus avoiding increased device complexity.
3Measurement precision
If iterative correction with error code generation is implemented, then duty cycle alignment precision is improved, but the operation time increases
Solution Approach 1:
The duty cycle correction circuit performs preliminary correction based on initial error codes before final detection and confirmation. This preliminary action allows the system to quickly approach the target duty cycle value, reducing the number of iterative cycles needed and thereby minimizing the time loss while maintaining high alignment precision.
Solution Approach 2:
The iterative correction process skips unnecessary intermediate steps by directly generating error codes that indicate the required correction amount. The system rushes through the correction process by using the error code to directly adjust the duty cycle in large steps when far from the target, and only performs fine adjustments when close to the target value, thus reducing overall correction time while maintaining precision.
Data Source
AI summary
A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided. The clock correction circuit comprises a delay-locked loop circuit configured to receive a first clock signal and generate a second clock signal obtained by delaying the first clock signal; a first duty cycle correction circuit configured to receive the second clock signal and generate a first correction clock signal obtained by correcting a duty cycle of the second clock signal; and a duty cycle detection circuit which includes a second duty cycle correction circuit and an error code generation circuit, wherein the error code generation circuit receives the first correction clock signal, and generates a first error code as to whether to correct the duty cycle of the second clock signal on the basis of the first correction clock signal, the second duty cycle correction circuit generates a second correction clock signal obtained by correcting the duty cycle of the first correction clock signal in response to the first error code, the error code generation circuit generates a second error code as to whether to correct the duty cycle of the second clock signal on the basis of the second correction clock signal, and the first duty cycle correction circuit receives the second error code, and generates a third correction clock signal obtained by correcting the duty cycle of the second clock signal in response to the second error code.