Clock Duty Cycle Correction by Independent Falling-Edge Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Integrating duty cycle correction circuits within phase-locked loop control loops can interfere with the operation of phase-locked loops due to simultaneous adjustment of both rising and falling edges of the clock signal, affecting phase lock and duty cycle alignment.
Innovation Solution
A duty cycle correction circuit that adjusts the falling edge of the clock signal independently, using a pulse generator, voltage-controlled delay circuit, and edge adjustment circuit to achieve a desired duty cycle without interfering with the phase-locked loop's operation, by generating a pulse in response to the falling edge and adjusting the control voltage based on the duty cycle difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty cycle correction circuit adjusts both rising and falling edges of the clock signal, then the desired duty cycle is achieved, but the phase-locked loop operation is interfered with
Solution Approach 1:
The duty cycle correction function is segmented into two independent parts: the rising edge is controlled by the PLL while the falling edge is controlled by the DCC circuit. This segmentation allows each circuit to control only its designated edge without interfering with the other, resolving the contradiction between duty cycle accuracy and phase lock stability
Solution Approach 2:
Different control strategies are applied to different parts of the clock signal: the PLL controls the rising edge for phase alignment while the DCC circuit controls the falling edge for duty cycle correction. This local differentiation allows each circuit to optimize its function without disrupting the overall system
2Manufacturing precision
If the DCC circuit is integrated into the PLL control loop, then duty cycle correction is achieved, but interference with PLL operation occurs
Solution Approach 1:
The control loop is segmented into two independent pathways: the PLL control loop handles rising edge phase alignment while the DCC control loop handles falling edge duty cycle correction. This segmentation eliminates interference between the two control functions while maintaining both corrections
Solution Approach 2:
The DCC circuit acts as an intermediary that receives the PLL output and independently adjusts the falling edge without disrupting the PLL's rising edge control. This intermediary approach allows duty cycle correction to be added without interfering with the existing PLL operation
Data Source
AI summary
In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.