Clock Signal Duty-Cycle Control Using Feedback Threshold Adjustment

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing circuit arrangements for providing clock signals with adjustable duty cycles lack precise control and stability, particularly in the presence of disturbances or electrical loads, which can affect the accuracy of the duty cycle.

Innovation Solution

A circuit arrangement comprising an amplifier circuit, a low-pass filter, and an integrator circuit, where the integrator circuit provides a threshold value for controlling the duty cycle, and feedback mechanisms ensure that any changes in the duty cycle are counteracted, maintaining the original duty cycle accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If existing circuit arrangements are used for providing clock signals, then basic clock signal generation is achieved, but precise control and stability of the duty cycle cannot be maintained under disturbances or electrical loads

Engineering Contradiction:
Improveduty cycle accuracyVSAvoidduty cycle stability under disturbances
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the clock signal is fed back through a low-pass filter and integrator circuit to generate a threshold value that is compared with the oscillator signal. This closed-loop feedback system continuously monitors and adjusts the duty cycle, ensuring precise control and stability even under disturbances or electrical loads by counteracting any deviations from the desired duty cycle.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces an integrator circuit as an intermediary element between the low-pass filter and the comparator. This integrator circuit processes the feedback signal and generates a stable threshold value that mediates the comparison process, enabling precise duty cycle control by smoothing out variations and providing a stable reference for the comparator to maintain accurate duty cycle under varying conditions.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If simple circuit arrangements are used, then device complexity is reduced, but precise adjustment and stabilization of the duty cycle cannot be achieved

Engineering Contradiction:
Improveduty cycle adjustment precisionVSAvoidcircuit arrangement complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the duty cycle control function into distinct modular components: an amplifier circuit for signal conditioning, a low-pass filter for noise reduction and signal smoothing, and an integrator circuit for threshold value generation. This segmentation allows each component to perform its specific function with high precision while maintaining overall system manageability and adjustability through individual component optimization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs dynamic elements including an adjustable threshold value mechanism and a buffer with inverter(s) that can adapt their operation based on the feedback signal. The integrator circuit dynamically adjusts the threshold value in response to duty cycle deviations, and the buffer dynamically compensates for phase shifts, enabling precise duty cycle adjustment and stabilization through dynamic adaptation rather than fixed parameters.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7786777B2Circuit arrangement and method for the provision of a clock signal with an adjustable duty cycle
Publication Date: 2010.08.31 AUSTRIAMICROSYSTEMS AG
  • US7786777B2 patent drawing
  • US7786777B2 patent drawing
  • US7786777B2 patent drawing

AI summary

The circuit arrangement (1) comprises an input (2) for the connection of an oscillator (3) and an amplifier circuit (20) having a first input (21) that is coupled to the input (1) of the circuit arrangement (1), having a second input (22) and an output (23) that is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty cycle (φ) can be accessed at the output (4) of the circuit arrangement (1). The circuit arrangement (1) furthermore incorporates a low-pass filter (40), the input of which is connected to the output (23) of the amplifier circuit (20), and an integrator circuit (50) the input of which is connected to the low-pass filter (40) and the output of which is connected to the second input (22) of the amplifier circuit (20) for the delivery of an adjustable threshold value (Vth) for controlling the duty cycle (φ).