Clock Duty Cycle Adjustment for Robust Cross-Domain Level Shifting
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) become smaller and more complex, the decreasing operating voltages affect their performance, particularly in level shifter circuits that operate across different voltage domains, leading to challenges in maintaining accurate clock duty cycles and robustness against corrupted input waveforms.
Innovation Solution
A clock duty cycle adjustment and calibration circuit is introduced, comprising a ring oscillator, level shifters, a duty cycle adjustment circuit, and a duty cycle calibration circuit. This circuit generates and adjusts phase clock signals across different voltage domains, calibrates duty cycles independently of input phase clock signals, and uses filters with higher frequencies to occupy less area, thereby enhancing robustness and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional frequency dividers are used to generate clock signals, then frequency division is achieved, but the circuit area increases and complexity increases
Solution Approach 1:
The patent replaces traditional mechanical frequency divider circuits with a ring oscillator-based system that generates clock signals through oscillation and phase manipulation. The ring oscillator uses a feedback loop with odd number of inverting stages to generate continuous oscillations, eliminating the need for complex frequency division logic and reducing circuit area.
Solution Approach 2:
The patent changes the operating parameters by using differential voltage swings and phase modulation to achieve frequency division functionality. By manipulating the phase difference between differential clock signals and using duty cycle adjustment, the system achieves the same frequency division effect with simpler circuitry.
2Measurement precision
If duty cycle adjustment is performed using complex calibration circuits, then accurate duty cycle is achieved, but the circuit area increases
Solution Approach 1:
The duty cycle calibration circuit uses the circuit's own output signals to perform self-calibration. The calibration process feeds back a portion of the generated clock signal through the duty cycle adjustment circuit, allowing the system to automatically adjust and optimize its own duty cycle without requiring external calibration equipment or additional complex control logic.
3Adaptability or versatility
If level shifters operate across different voltage domains, then voltage domain compatibility is achieved, but robustness against corrupted input waveforms deteriorates
Solution Approach 1:
The differential ring oscillator design inherently provides immunity to single-event upsets and corrupted input waveforms by using complementary signal paths. The differential structure ensures that noise or corruption on one signal line is compensated by the opposite change on the complementary line, maintaining signal integrity across voltage domains before the corruption can affect operation.
Data Source
AI summary
A clock circuit includes a set of level shifters, and adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle, and is coupled to the adjustment circuit. The adjustment circuit is configured to generate a first clock output signal responsive to a first phase clock signal and a second phase clock signal of the first set of phase clock signals, and adjust the first clock output signal and a second duty cycle of the first clock output signal responsive to a set of control signals. The calibration circuit is coupled to the adjustment circuit, and configured to perform a duty cycle calibration of the second duty cycle of the first clock output signal based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration.