Duty Cycle Detection Circuit for Stable Comparator Offset Correction
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Solution Overview
Problem
Existing duty cycle detection circuits in semiconductor circuits face accuracy issues due to process variations, leading to offsets that affect the accuracy of duty cycle correction, particularly in semiconductor memories where data input/output timing relies on precise clock signal duty control.
Innovation Solution
A duty cycle detection circuit comprising an input switching unit and a comparator, along with offset control logic, which generates offset adjustment codes by comparing duty detection signals from different signal combinations to adjust the input terminal offsets, ensuring stable compensation and accurate duty cycle correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a duty cycle detection circuit is used to detect the duty of clock signals, then duty cycle detection capability is provided, but offset due to process variation reduces measurement precision
Solution Approach 1:
The patent implements a feedback mechanism where the duty cycle detection circuit continuously monitors the duty cycle of clock signals and feeds back correction information to adjust for offsets. The circuit compares the detected duty cycle with the target duty cycle and generates correction signals that are fed back to the clock signal generation or distribution path, thereby dynamically compensating for process variation-induced offsets and maintaining accurate duty cycle measurement.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting circuit parameters such as threshold voltages, reference signal levels, or timing delays based on detected duty cycle deviations. The duty cycle detection circuit modifies these parameters in real-time to compensate for process variations, ensuring that the measurement precision remains high despite manufacturing tolerances and environmental changes.
2Manufacturing precision
If duty cycle correction is implemented to ensure accurate timing, then data input/output timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the duty cycle detection function with the correction function into a single integrated circuit block. The duty cycle detection circuit and the correction mechanism are combined such that the same circuit structure performs both detection and correction operations, reducing the overall device complexity while maintaining accurate data input/output timing.
Solution Approach 2:
The patent designs the duty cycle detection circuit to serve multiple functions: it detects the duty cycle of clock signals, generates correction signals, and applies corrections to maintain timing accuracy. This multi-functional approach eliminates the need for separate dedicated correction circuits, thereby reducing device complexity while achieving precise data timing control.
Data Source
AI summary
Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.