Clock Generation Circuit Using Duty-Based Multiphase Phase Correction
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Solution Overview
Problem
High-speed semiconductor apparatuses face challenges in accurately generating and synchronizing multiphase clock signals due to phase differences, which affect data output reliability and speed.
Innovation Solution
A clock generation circuit that includes a reference clock generator, triggering unit, pulse detector, correction code generator, and offset code generator to estimate and correct phase offsets in multiphase clock signals, ensuring accurate synchronization and data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiphase clock signals are generated by dividing the internal clock, then data output speed is improved, but phase differences affect data output reliability
Solution Approach 1:
The patent implements a feedback mechanism where the duty detection signal generated from phase differences between multiphase clock signals is fed back to adjust the correction code. This closed-loop feedback system continuously monitors and corrects phase deviations, ensuring that data output reliability is maintained even at high speeds where phase differences would normally degrade performance.
Solution Approach 2:
The patent dynamically changes the correction code parameter based on the duty detection signal to compensate for phase differences. By adjusting the correction code in response to detected phase variations, the system maintains accurate timing synchronization across all multiphase clock signals, thereby preserving data output reliability while operating at high speeds.
2Reliability
If phase correction is performed on multiphase clock signals, then data output reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the phase correction function into distinct modular components: a pulse detector that generates duty detection signals from phase differences, a correction code generator that processes these signals, and an offset code generator that applies corrections. This segmentation allows each component to perform a specific function efficiently, reducing overall circuit complexity while maintaining reliable phase correction capability.
Solution Approach 2:
The patent introduces intermediate signals (duty detection signals and correction codes) that mediate between the raw phase differences and the final phase-corrected multiphase clock signals. These intermediary elements simplify the correction process by breaking it down into manageable steps, reducing the complexity of direct phase correction while ensuring reliable timing synchronization.
3Measurement precision
If duty detection is performed based on phase difference, then phase accuracy is improved, but measurement precision requirements increase
Solution Approach 1:
The patent replaces complex direct phase difference measurement with a duty cycle detection mechanism. Instead of directly measuring and comparing phase angles, the system converts phase differences into duty cycle variations of detection signals, which are then processed to generate correction codes. This substitution simplifies the measurement process while maintaining high phase measurement accuracy.
Solution Approach 2:
The patent transforms the phase difference parameter into a duty cycle parameter for detection purposes. By measuring duty cycle variations instead of directly measuring phase angles, the system reduces the difficulty of detection while maintaining measurement precision. The duty detection signal serves as an intermediate representation that is easier to measure accurately than direct phase differences.
Data Source
AI summary
A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a triggering unit configured to generate a pair of second reference clocks from the pair of first reference clocks, a pulse detector configured to generate a duty detection signal based on a phase difference between the pair of second reference clocks, a correction code generator configured to generate a reference correction code based on the duty detection signal, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.