Clock Synthesizer Duty Cycle Correction With Phase Interpolation

Solution Overview

Problem

Existing methods for correcting duty cycle errors in clock signals are inefficient, requiring lengthy iterative adjustments and consuming high power, and are unable to correct errors quickly enough for rapidly rising system clock speeds.

Innovation Solution

A Duty Cycle Corrected Phase Interpolator (DCCPI) circuit that adjusts both phase and duty cycle of a clock signal in a single loop using a Phase Locked Loop (PLL), buffer, and clock tree, with digital and analog control, to achieve a nearly 50% duty cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If iterative adjustment of delay circuits is used to correct duty cycle error, then duty cycle accuracy is improved, but correction time becomes excessively long

Engineering Contradiction:

Improveduty cycle accuracyVSAvoidcorrection time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, thereby achieving both high accuracy and fast correction speed simultaneously

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, thereby achieving both high accuracy and fast correction speed simultaneously

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If iterative duty cycle correction methods are used, then duty cycle precision is improved, but power consumption increases

Engineering Contradiction:

Improveduty cycle precisionVSAvoidpower consumption

Core Design Contradiction:

Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, thereby achieving both high accuracy and fast correction speed simultaneously

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the iterative mechanical adjustment process with a digital lookup table approach. Instead of continuously adjusting delay circuits through multiple iterations, the system uses pre-computed values stored in memory, eliminating the need for repeated measurements and adjustments, thus significantly reducing power consumption while maintaining high precision

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Manufacturing precision

If known duty cycle correction approaches are used, then duty cycle control is achieved, but the circuit becomes complicated and power consumption increases

Engineering Contradiction:

Improveduty cycle controlVSAvoidcircuit complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores optimal delay values in a lookup table before operation. When duty cycle correction is needed, the system directly retrieves the pre-computed delay value instead of performing iterative adjustments, thereby achieving both high accuracy and fast correction speed simultaneously

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent replaces the iterative mechanical adjustment process with a digital lookup table approach. Instead of continuously adjusting delay circuits through multiple iterations, the system uses pre-computed values stored in memory, eliminating the need for repeated measurements and adjustments, thus significantly reducing power consumption while maintaining high precision

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12136925B2Clock synthesizer

Publication Date: 2024.11.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A clock synthesizer is provided. The Clock synthesizer includes a a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer is configured to store the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit is configured to receive the clock signal from the clock buffer, adjust a duty cycle of the clock signal to substantially equal to 50%, perform phase interpolation on the clock signal, and provide the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.