Clock Duty Cycle Correction Using Prime-Ratio Sampling
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Solution Overview
Problem
Existing techniques for correcting clock duty cycles in DDR memory systems are either too slow, large, or inaccurate, particularly when dealing with multiple clock signals, and conventional asynchronous sampling methods can introduce significant errors due to non-random sampling assumptions.
Innovation Solution
A duty cycle correction circuitry that uses a well-controlled asynchronous sampling clock to periodically sample the target clock signal at discrete, equally spaced points based on a prime number ratio of the reference clock frequency, allowing for precise measurement and correction of duty cycle errors in a single measurement cycle, thereby improving accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If RC filter is used to correct clock duty cycle, then duty cycle precision is improved, but correction speed becomes too slow and device size increases
Solution Approach 1:
The patent replaces the RC filter-based correction mechanism with a delay-locked loop (DLL) based correction mechanism. The DLL uses digital logic and feedback control to achieve duty cycle correction without the inherent speed limitations of RC time constants, thereby improving correction speed while maintaining precision.
Solution Approach 2:
The patent implements a feedback mechanism where the measured duty cycle is compared against a target duty cycle, and the difference is used to adjust the clock signal through the DLL. This closed-loop feedback enables precise and rapid correction by continuously monitoring and adjusting the duty cycle based on actual measurements.
2Measurement precision
If RC filter is used to correct clock duty cycle, then duty cycle precision is improved, but device area increases
Solution Approach 1:
The patent replaces the physically large RC filter components with compact digital logic circuits implemented in the DLL. This substitution dramatically reduces the device area required for duty cycle correction while maintaining the precision benefits through digital measurement and control mechanisms.
3Speed
If asynchronous sampling is used to measure duty cycle, then measurement speed is improved, but measurement accuracy deteriorates due to non-random sampling errors
Solution Approach 1:
The patent uses feedback to compare the measured duty cycle against a known target duty cycle and calculates the actual error. This feedback mechanism compensates for any systematic sampling errors by using the difference between measured and target values to drive the correction, thereby maintaining high accuracy despite asynchronous sampling.
Solution Approach 2:
The patent changes the sampling strategy by using a synchronous sampling clock that is phase-aligned with the target clock signal. This parameter change in the sampling methodology eliminates the non-random sampling errors inherent in asynchronous sampling while maintaining high measurement speed through coordinated timing.
Data Source
AI summary
Examples may include techniques for using a sample clock to measure a duty cycle by periodic sampling a target clock signal based on a prime number ratio of a reference clock frequency. The reference clock frequency used to set a measurement cycle time over which the duty cycle is to be measured. A magnitude of a duty cycle error as compared to a programmable target duty cycle is determined based on the measured duty cycle and the duty cycle is adjusted based, at least in part, on the magnitude of the duty cycle error.