Clock Duty Cycle Monitoring Using Phase-Diverse Random Sampling
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Solution Overview
Problem
Existing methods for monitoring clock duty cycles in VLSI digital circuits are inefficient, requiring infinite sampling times for high precision and being inaccurate when the clock is random or of low precision.
Innovation Solution
A system comprising a basic monitoring circuit and additional monitoring circuits, each sampling the clock signal with a random clock signal of adjusted phase, allowing for accurate duty cycle determination without infinite sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If probability statistics-based sampling method is used to monitor clock duty cycles, then the monitoring can be implemented with simple circuitry, but the sampling times must approach infinity to obtain high precision duty cycles
Solution Approach 1:
The patent divides the monitoring system into multiple independent monitoring circuits, each using a different random clock signal with distinct phase characteristics. This segmentation allows parallel sampling with fewer total samples needed compared to a single circuit requiring infinite sequential sampling.
Solution Approach 2:
The patent introduces phase dimension by using multiple random clock signals with different phases to sample the monitored clock. This adds a temporal dimension to the sampling process, enabling accurate duty cycle measurement with finite samples by exploiting phase diversity.
2Ease of operation
If probability statistics-based sampling method is used with random clock signals, then the monitoring can be implemented, but the precision deteriorates when the random clock precision is not perfect
Solution Approach 1:
The patent employs feedback mechanisms where each monitoring circuit's output is processed and combined with others. The calculation module uses feedback from multiple phase-diverse samples to compensate for individual clock precision errors, achieving accurate duty cycle measurement even when individual random clocks have limited precision.
Solution Approach 2:
The patent changes the phase parameter of random clock signals across different monitoring circuits. By varying this parameter systematically, the system captures duty cycle information from multiple perspectives, enabling accurate reconstruction even when individual sampling clocks have precision limitations.
3Device complexity
If single random clock signal is used for monitoring, then the circuit structure is simple, but the monitoring accuracy is insufficient for distorted clock duty cycles
Solution Approach 1:
The patent merges outputs from multiple monitoring circuits that each use differently-phased random clock signals. By combining these diverse samples in the calculation module, the system achieves superior monitoring accuracy for distorted duty cycles compared to any single circuit, while maintaining reasonable overall complexity through systematic integration.
Data Source
AI summary
An improved system for monitoring clock duty cycles, comprising: a first monitoring circuit configured to record a first quantity of high levels of the monitored clock signal sampled by a first random clock signal; a second monitoring circuit configured to record a second quantity of high levels of the monitored clock signal sampled by a second random clock signal, wherein the phase of the second random clock is adjusted by a second adjustment degree based on a first clock; a third monitoring circuit configured to record a third quantity of high levels of the monitored clock signal sampled by a third random clock signal, wherein the phase of the third random clock is the reverse of that of the first random clock; and a calculation module configured to determine a duty cycle of the monitored clock based on the first quantity, the second quantity, and the third quantity.