Clock Duty Rate Detection Circuit for Accurate 50:50 Timing
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Solution Overview
Problem
Conventional duty rate correction circuits in semiconductor devices face challenges in accurately detecting and maintaining a 50:50 duty rate of clock signals due to differences in the number of discharges during the logic high and low durations, leading to unreliable data output.
Innovation Solution
A duty rate detection circuit that includes a duty rate discharge unit for synchronized discharging during both logic durations, a level detection unit for voltage level comparison, and an output unit for generating a synchronized discharge detection signal, ensuring equal discharge counts for accurate duty rate detection and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional duty rate correction circuits are used to detect duty rate, then the circuit can operate at high frequencies, but the detection accuracy deteriorates due to differences in discharge counts during logic high and low durations
Solution Approach 1:
The patent applies preliminary action by pre-charging capacitors to a reference voltage level before the discharge phase. This ensures that both capacitors start from the same voltage state, eliminating cumulative errors from previous cycles and ensuring accurate duty rate detection even at high frequencies where timing margins are tight.
Solution Approach 2:
The patent replaces the conventional discharge-counting mechanism with a voltage-level comparison mechanism. Instead of counting discrete discharge events, the circuit measures the final voltage levels of capacitors after synchronized discharge periods, providing higher precision duty rate detection that is not limited by integer counting constraints.
2Device complexity
If the duty rate detection circuit uses different discharge counts for logic high and low durations, then the circuit structure is simplified, but the detection reliability deteriorates
Solution Approach 1:
The patent applies local quality by making the discharge operation symmetric (same discharge resistance and capacitance values) only for the measurement phase, while allowing asymmetric charge phases. This localized symmetry in the critical measurement portion ensures reliable duty rate detection without requiring complete symmetry throughout the entire circuit operation.
Solution Approach 2:
The patent uses feedback by comparing the voltage levels of two capacitors that have been discharged for equal durations, and using this comparison result to generate the duty rate detection signal. This feedback mechanism ensures that the detection is based on actual measured differences rather than assumed or counted values, improving reliability.
3Productivity
If the clock signal frequency is increased to improve operation rate, then the productivity increases, but the duty rate control difficulty increases making accurate detection harder
Solution Approach 1:
The patent uses periodic action by implementing periodic charging and discharging cycles of capacitors synchronized with the clock signal edges. This periodic operation allows the circuit to maintain accurate duty rate detection at high frequencies by resetting and repeating the measurement process at each clock cycle, preventing error accumulation.
Solution Approach 2:
The patent applies preliminary action by pre-charging capacitors to a known reference voltage before each discharge phase. This preliminary preparation ensures that each measurement cycle starts from a consistent state, enabling accurate duty rate detection even at high operating frequencies where there is limited time for each measurement cycle.
Data Source
AI summary
A duty rate detection circuit includes a duty rate detection block suitable for outputting a duty rate detection signal by detecting a duty rate of a clock signal having a first logic duration and a second logic duration and an output control block suitable for comparing the number of the first logic duration and the number of the second logic duration for a detection period and controlling an output moment of the duty rate detection signal.