Spread Spectrum Clock Modulation With Duty Ratio Correction

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Solution Overview

Problem

In semiconductor integrated circuits, the increasing integration speed and component density lead to electromagnetic interference (EMI) issues due to electromagnetic wave radiation, causing duty ratio distortion and signal errors, which existing spread spectrum clock generators fail to adequately address.

Innovation Solution

A clock modulation circuit with a correction unit that adjusts the duty ratio by delaying the rising and falling timings of the modulated clock, using a modulation block with switching and impedance elements driven by control signals to generate a modulated clock with a uniform duty ratio and dispersed EMI.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If spread spectrum processing is performed to modulate operation clock frequency, then EMI radiation is reduced, but duty ratio distortion occurs causing signal errors

Engineering Contradiction:
ImproveEMI radiationVSAvoidsignal error rate
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the duty ratio of the modulated clock is detected and compared against a target value, and the spread spectrum modulation parameters are adjusted based on this comparison to maintain the desired duty ratio while reducing EMI

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes modulation parameters including modulation depth, modulation frequency, and duty ratio correction factors to optimize both EMI reduction and signal integrity under different operating conditions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If operation frequency is increased to improve integration speed, then processing capability is improved, but EMI radiation increases

Engineering Contradiction:
Improveintegration speedVSAvoidEMI radiation
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent employs dynamic frequency modulation where the clock frequency is varied within a range rather than operating at a fixed high frequency, thereby maintaining processing speed while spreading EMI energy across multiple frequencies to reduce peak radiation

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses periodic spread spectrum modulation to vary the clock frequency in a controlled periodic manner, which maintains average processing throughput while distributing electromagnetic energy over time and frequency to reduce harmful radiation

Inventive Principle:
Principle #19Periodic action

3Reliability

If duty ratio correction is applied to prevent signal errors, then signal reliability is improved, but circuit complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces intermediary duty ratio correction circuits that act as mediators between the spread spectrum modulator and the system clock distribution network, correcting duty ratio distortion without requiring complex redesign of the entire clock system

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the clock system into separate functional segments including the spread spectrum modulator, duty ratio detection circuit, and correction circuitry, allowing independent optimization and simplification of each segment while achieving overall system reliability

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7616038B2Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same
Publication Date: 2009.11.10 SK HYNIX INC
  • US7616038B2 patent drawing
  • US7616038B2 patent drawing
  • US7616038B2 patent drawing

AI summary

A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.