Clock Generation Circuit for Stable Duty Ratio and Cross-Point
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Solution Overview
Problem
Existing semiconductor clock generation circuits, particularly ring oscillators, face challenges in maintaining a constant duty ratio and centered cross-point of clock signals due to variations in power voltage, temperature, and transistor characteristics, leading to distorted output signals that can narrow the effective window for data operation.
Innovation Solution
A clock generation circuit comprising a preliminary clock generation circuit, a clock doubler circuit, and an edge trigger circuit that generates preliminary clock signals with half the target cycle, doubles their cycles to produce intermediate signals, and triggers these signals to output clock signals with a target cycle, ensuring a constant duty ratio and centered cross-point, thereby reducing signal skew and maintaining high-speed data operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a ring oscillator is used to generate clock signals, then the circuit structure is simple, but the duty ratio of the output signal changes due to power voltage variations
Solution Approach 1:
The clock generation circuit is divided into multiple independent functional blocks: a ring oscillator for frequency generation, a duty ratio correction circuit for stabilization, and a cross-point adjustment circuit for centering. This segmentation allows each block to perform its specific function optimally while maintaining overall system reliability.
Solution Approach 2:
The patent introduces intermediate circuits between the ring oscillator and the final output: a duty ratio correction circuit that uses current mirrors and switching elements to equalize high and low pulse widths, and a cross-point adjustment circuit that shifts the timing center. These intermediary circuits act as mediators that correct the raw oscillator output without requiring fundamental changes to the oscillator itself.
2Reliability
If power voltage variations occur, then the duty ratio of clock signals becomes distorted, but adding correction circuits increases device complexity
Solution Approach 1:
The duty ratio correction circuit changes the electrical parameters of the clock signal by using controlled current sources and switching elements to equalize the high and low pulse widths. By adjusting current magnitudes and switching timings, the circuit transforms the distorted duty ratio into a stable 50% duty ratio while maintaining compatibility with the existing ring oscillator structure.
3Productivity
If the cross-point of clock signals is not centered, then the effective window for data operation is narrowed, but adjusting the cross-point requires additional circuit elements
Solution Approach 1:
The cross-point adjustment circuit performs preliminary timing alignment on the clock signals before they reach the data operation stage. By pre-centering the cross-point using delay elements and switching circuits, the circuit ensures that the optimal data operation window is established in advance, maximizing productivity without requiring complex real-time adjustments.
Data Source
AI summary
A clock generation circuit includes: a preliminary clock generation circuit suitable for generating a first preliminary clock signal with a half of a target cycle, and generating a second preliminary clock signal by inverting the first preliminary clock signal; a clock doubler circuit suitable for generating first and second intermediate clock signals by respectively doubling the cycles of the first and second preliminary clock signals; and an edge trigger circuit suitable for triggering the first and second intermediate clock signals to output first and second output clock signals with the target cycle, respectively, according to the first and second preliminary clock signals.