Clock Duty Ratio Correction Using Ramp-Based Regeneration
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Solution Overview
Problem
Existing clock signal duty ratio correction circuits in daisy chain topologies require complex circuitry, leading to increased manufacturing costs and reduced communication quality due to asymmetry in clock signals.
Innovation Solution
A clock signal duty ratio correction circuit that includes a period indication signal generation circuit, first and second ramp signal generation circuits, and a clock signal regeneration circuit to generate a clock regeneration signal with a target duty ratio, utilizing capacitors and currents to maintain duty ratio symmetry without complex additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logic inverters are used in each stage of operation circuits in a daisy chain topology, then signal transmission and logic inversion are achieved, but the clock signal duty ratio becomes asymmetrical and deteriorates with each stage
Solution Approach 1:
A duty ratio correction circuit is introduced as an intermediary component between stages of operation circuits. This correction circuit receives the asymmetrical clock signal, corrects its duty ratio using a correction signal generated by comparing the clock signal with a reference signal, and outputs a corrected clock signal with restored duty ratio symmetry, thereby preventing duty ratio deterioration in the daisy chain topology
Solution Approach 2:
The duty ratio correction circuit employs feedback mechanisms where the clock signal is compared with a reference signal to generate a correction signal. This correction signal is fed back to adjust the clock signal's duty ratio, creating a closed-loop system that continuously maintains duty ratio symmetry despite signal transmission through multiple logic inverter stages
2Manufacturing precision
If complex circuitry is added to correct duty ratio changes, then duty ratio symmetry is maintained, but manufacturing costs increase
Solution Approach 1:
The duty ratio correction circuit is designed with multi-functionality, serving both signal transmission and duty ratio correction functions within a single integrated circuit block. This universal approach eliminates the need for separate complex correction circuits at each stage, reducing overall device complexity while maintaining duty ratio symmetry
Solution Approach 2:
The correction circuit operates by changing parameters of existing signals rather than adding complex hardware. It generates a correction signal by comparing timing parameters of the clock signal with a reference signal, then uses this correction signal to adjust the duty ratio parameter, achieving precision correction through parameter manipulation rather than complex circuit architecture
Data Source
AI summary
A clock signal duty ratio correction circuit includes: a period indication signal generation circuit configured to operably generate a period indication signal according to a clock signal, wherein a period indication level of the period indication signal is correlated with a period time of the clock signal; a first ramp signal generation circuit configured to operably generate a first ramp signal according to the clock signal; and a clock signal regeneration circuit configured to operably generate a clock regeneration signal according to a triggering of the clock signal and according to a comparison between the first ramp signal and the period indication level, such that the clock regeneration signal has a target duty ratio; wherein a slope of the first ramp signal is correlated with the target duty ratio.