Clock Duty Cycle Tuning for RF Spur Suppression in Multi-Radio SoCs
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Solution Overview
Problem
In multiple radio system on chip (SoC) devices, digital circuits cause interference with RF signals due to harmonics of the digital clock signal falling within the RF frequency band, leading to reduced call reliability and dropped connections, with existing solutions like frequency planning and clock dither techniques impacting throughput and adding complexity.
Innovation Solution
A digital system comprising a spur calculator, duty cycle computation module, and clock generator that computes and suppresses the amplitude of harmonics interfering with RF signals by varying the duty cycle of the digital clock signal, ensuring equal current profiles in positive and negative clock edges to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If frequency planning approach is used to avoid digital clock harmonics interfering with RF signals, then interference is reduced, but system throughput is affected due to high frequency operation
Solution Approach 1:
The patent changes the duty cycle parameter of the digital clock signal from the conventional 50% to a non-50% value (e.g., 60% or 40%). This parameter modification shifts the spectral distribution of the clock harmonics, moving them away from the RF frequency bands of interest. The duty cycle computation module calculates the optimal duty cycle value that minimizes interference while maintaining system throughput, thereby resolving the contradiction between reducing digital interference and preserving productivity.
2Object-affected harmful factors
If clock dither technique is used to spread the spectrum of the power profile, then interference is reduced, but extra complexity is added to the circuit
Solution Approach 1:
The patent extracts and eliminates the unnecessary complexity from the clock dither technique by replacing it with a simpler duty cycle modulation approach. Instead of adding jitter to the clock signal to spread the spectrum, the invention directly modifies the duty cycle parameter of the clock signal. This extraction of the essential function (spectrum shaping) while removing the complex implementation (jitter injection circuitry) reduces device complexity while maintaining interference suppression effectiveness.
3Object-affected harmful factors
If high frequency operation is selected to avoid frequency band conflicts, then interference is reduced, but timing and area are impacted
Solution Approach 1:
The patent changes the duty cycle parameter to achieve frequency conflict avoidance without increasing clock frequency or chip area. By adjusting the duty cycle away from 50%, the harmonic spectrum of the digital clock is reshaped, pushing the interfering harmonics away from RF bands. This allows the system to maintain lower clock frequencies and smaller chip areas while still avoiding frequency conflicts, thereby resolving the contradiction between reducing frequency conflicts and minimizing area.
Data Source
AI summary
A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed.