Duty Cycle Correction Circuit With Selective High-Period Switching
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Solution Overview
Problem
Digital-type duty cycle correcting circuits face limitations in achieving improved duty ratio quality, particularly in high-speed, highly integrated semiconductor integrated circuits, where they struggle to match the performance of analog-type circuits in terms of duty ratio correction while maintaining low power consumption and small area occupancy.
Innovation Solution
A digital-type duty cycle correcting circuit is designed with a first and second duty ratio correcting unit that widen or narrow the high-level period of an input clock based on detection signals, a clock selecting unit to output the corrected clock, and a duty ratio detecting unit to generate detection signals, enabling selective output of corrected clocks with improved duty ratio quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an analog-type duty cycle correcting circuit is used, then duty ratio quality is improved, but operation time increases, area occupancy increases, and current consumption increases
Solution Approach 1:
The patent replaces the analog-type duty cycle correcting circuit with a digital-type circuit that uses logic operations (AND, OR, NOT) and delay elements to achieve duty ratio correction. This substitution of digital logic for analog circuitry maintains improved duty ratio quality while reducing operation time, area occupancy, and current consumption.
Solution Approach 2:
The patent changes the operating parameters by using digital signal levels and logic states instead of continuous analog voltages. The duty ratio correction is achieved through controlled logic operations and time delays rather than analog component adjustments, enabling faster operation and lower power consumption while maintaining correction quality.
2Manufacturing precision
If an analog-type duty cycle correcting circuit is used, then duty ratio quality is improved, but area occupancy increases
Solution Approach 1:
The patent replaces the analog-type duty cycle correcting circuit with a digital-type circuit that uses logic operations (AND, OR, NOT) and delay elements to achieve duty ratio correction. This substitution of digital logic for analog circuitry maintains improved duty ratio quality while reducing operation time, area occupancy, and current consumption.
Solution Approach 2:
The patent segments the duty ratio correction function into discrete digital logic operations and delay stages. By dividing the correction process into separate logic blocks that can be independently implemented and optimized, the overall circuit area is reduced compared to a monolithic analog correction circuit while maintaining the required correction precision.
3Manufacturing precision
If an analog-type duty cycle correcting circuit is used, then duty ratio quality is improved, but current consumption increases
Solution Approach 1:
The patent replaces the analog-type duty cycle correcting circuit with a digital-type circuit that uses logic operations (AND, OR, NOT) and delay elements to achieve duty ratio correction. This substitution of digital logic for analog circuitry maintains improved duty ratio quality while reducing operation time, area occupancy, and current consumption.
Solution Approach 2:
The patent employs periodic clock signals and time-delayed feedback mechanisms to achieve duty ratio correction through discrete timing intervals rather than continuous analog processing. This periodic digital operation reduces average current consumption compared to continuously operating analog circuits while maintaining correction accuracy.
4Duration of action of moving object
If a digital-type duty cycle correcting circuit is used, then operation time is reduced, area occupancy is reduced, and current consumption is reduced, but duty ratio quality deteriorates
Solution Approach 1:
The patent replaces the analog-type duty cycle correcting circuit with a digital-type circuit that uses logic operations (AND, OR, NOT) and delay elements to achieve duty ratio correction. This substitution of digital logic for analog circuitry maintains improved duty ratio quality while reducing operation time, area occupancy, and current consumption.
Solution Approach 2:
The patent incorporates feedback mechanisms where the output clock signal is delayed and fed back to control logic operations that adjust the duty ratio. This closed-loop digital feedback enables precise duty ratio control comparable to analog circuits while maintaining the speed and power advantages of digital implementation.
Data Source
AI summary
A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the high-level period of the input clock in response to the detection signal, thereby correcting the duty ratio of the input clock to output a second corrected clock. A clock selecting unit selectively outputs the first corrected clock or the second corrected clock as an output clock in response to the detection signal. A duty ratio detecting unit detects a duty ratio of the output clock, thereby generating the detection signal.