Clock Network ECO Using Candidate Point Delay Optimization
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Solution Overview
Problem
Existing engineering change order (ECO) techniques for optimizing clock networks in integrated circuits (ICs) are resource- and time-inefficient, particularly when addressing timing violations across complex clock network topologies, often requiring weeks to complete and focusing primarily on leaf-level optimizations that do not fully address issues at all levels of the clock tree.
Innovation Solution
A method involving the selection of candidate clock points from a clock network and performing multi-step iterative testing of timing delay adjustment values, using enumeration and potentially machine learning, to optimize clock paths efficiently, reducing computational costs and time by focusing on key points across the entire clock network hierarchy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECO techniques are used to optimize clock networks, then timing violations can be addressed, but the process requires weeks to complete and is resource-inefficient
Solution Approach 1:
The patent segments the clock network optimization problem by dividing clock points into different hierarchical levels (leaf-level vs. non-leaf-level). Instead of treating all clock points uniformly, the method selectively applies optimization techniques to specific segments of the clock tree, enabling faster processing while maintaining effectiveness in resolving timing violations.
Solution Approach 2:
The patent extracts and addresses the most critical timing violations first by identifying clock points with the greatest impact on overall clock network performance. By taking out the most significant issues from the full set of timing violations and resolving them preferentially, the method achieves effective optimization in reduced time without addressing every single violation exhaustively.
2Reliability
If comprehensive optimization across all clock points is performed, then all timing violations are addressed, but computational resources and time increase significantly
Solution Approach 1:
The patent applies local quality by treating different regions of the clock network differently based on their characteristics. Leaf-level clock points receive one type of optimization treatment while non-leaf-level points receive another. This localized approach ensures that each segment receives appropriate optimization attention while avoiding the computational overhead of uniform comprehensive optimization across the entire clock network.
Solution Approach 2:
The patent implements partial action by focusing optimization efforts on the most critical clock points and timing violations rather than exhaustively optimizing every aspect of the clock network. By applying optimization to a selective subset of clock points that have the greatest impact on overall performance, the method achieves satisfactory results with significantly reduced computational resources and time.
3Manufacturing precision
If leaf-level optimizations are focused on, then local timing issues are resolved, but issues at higher levels of the clock tree are not fully addressed
Solution Approach 1:
The patent achieves universality by creating an optimization framework that can handle multiple types of clock points (leaf-level and non-leaf-level) within a single unified process. The method is designed to be multi-functional, adapting its optimization strategy based on the type of clock point being processed, thereby providing comprehensive coverage across the entire clock network hierarchy while maintaining precision for each specific case.
Data Source
AI summary
Methods and apparatus for obtaining timing adjustment values for clock points in a clock network are disclosed. In some embodiments, engineering change order (ECO) may be performed in a time- and resource-efficient manner by selecting candidate clock points from a plurality of clock points in the clock network, and performing enumerative and iterative tests on the selected candidate clock points to determine a combination of timing delay adjustment values that most reduces negative slack. The determined timing delay adjustment values may be implemented by an ECO system to effect changes to the clock network and reduce timing violations therein.