Clock Adjustment Circuit for Transmission Gate Edge Alignment
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Solution Overview
Problem
Conventional clock generation circuits face issues with misalignment of rising and falling edges in clocks due to process, voltage, and temperature variations, leading to non-simultaneous turning on or off of PMOS and NMOS transistors in transmission gates, which degrades the performance of sampling circuits.
Innovation Solution
A clock adjustment circuit that includes a control voltage generation circuit, AC coupling circuit, DC voltage generation circuit, and determination circuit, which adjusts the DC level of input clocks to generate output clocks with aligned rising and falling edges, using negative feedback and resistance values to equalize transistor turn-on resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional clock generation circuits are used to generate clocks for transmission gate control, then the circuit structure is simple, but the rising and falling edges of the clocks are not aligned due to process, voltage, and temperature variations, causing PMOS and NMOS transistors to not turn on/off simultaneously and degrading sampling circuit performance
Solution Approach 1:
The patent introduces a feedback mechanism where the clock adjustment circuit monitors the clock signals and dynamically adjusts the DC levels of the first and second clocks to compensate for process, voltage, and temperature variations. This feedback loop ensures that the rising and falling edges remain aligned, allowing PMOS and NMOS transistors to turn on/off simultaneously without requiring complex circuit restructuring
Solution Approach 2:
The patent changes the DC level parameter of the clock signals dynamically. By adjusting the DC levels of the first and second clocks based on detected variations, the circuit maintains proper edge alignment across different operating conditions. This parameter adjustment approach resolves the contradiction by adapting to variations rather than requiring a completely new circuit architecture
2Reliability
If the DC levels of input clocks are not adjusted, then the circuit operation is straightforward, but the transmission gate performance degrades due to non-simultaneous transistor switching
Solution Approach 1:
The patent introduces a clock adjustment circuit as an intermediary component between the conventional clock generation circuit and the transmission gate. This intermediary adjusts the DC levels of the clock signals to ensure proper alignment, thereby improving transmission gate reliability without requiring fundamental changes to the existing circuit architecture. The intermediary handles the complexity, keeping the overall system design manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves the linearity of sampling circuits by ensuring simultaneous turning on and off of PMOS and NMOS transistors, reducing sampling time constants and enhancing the tracking capability of input signals.
Implementation Method 1
The control voltage generation circuit includes a transistor and a reference resistor and is configured to generate a control voltage according to the reference resistor
Implementation Method 2
The AC coupling circuit is coupled between the input port and the output port
Implementation Method 3
The determination circuit is coupled to the output port, the control voltage generation circuit, and the DC voltage generation circuit, and is configured to couple the control voltage or the DC voltage to the output port according to the output clock pair
Data Source
AI summary
A sampling device includes a clock generation circuit, a clock adjustment circuit, and a sampling circuit. The clock generation circuit is configured to generate a first clock and a second clock according to a reference clock. The clock adjustment circuit is configured to adjust a direct current (DC) level of one of the first clock and the second clock to generate a third clock and a fourth clock. The sampling circuit is configured to sample an input signal according to the third clock and the fourth clock to generate an output signal. The sampling circuit includes a transmission gate. The transmission gate includes a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS transistor) and an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS transistor) that respectively receive the third clock and the fourth clock.