Clock-Edge Data Bridge for Unknown Phase Datapaths
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Solution Overview
Problem
Efficient communication between subsystems of integrated circuits is hindered by clock signal phase differences and delays, leading to potential data transmission failures, and existing solutions like FIFO buffers consume significant area and power.
Innovation Solution
The system detects phase differences between clock signals and selectively transmits data on either the rising or falling edge of the clock signal based on these differences, eliminating the need for intervening circuits beyond signal lines and passive connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FIFO buffer is used to ensure safe data transmission between subsystems with different clock phases, then data transmission reliability is improved, but the area consumption and power consumption increase significantly
Solution Approach 1:
The patent extracts and eliminates the FIFO buffer component from the system by implementing direct phase-aware data transmission. The transmitting subsystem detects the phase difference between clock signals and selectively transmits data on appropriate clock edges, removing the need for intermediate buffering storage and thereby reducing area consumption while maintaining transmission reliability.
Solution Approach 2:
The patent changes the transmission parameter from fixed-edge data transmission to variable-edge transmission based on detected phase differences. By detecting whether the phase difference is greater or less than 180 degrees and selectively using rising or falling edges for data transmission, the system achieves reliable communication without requiring FIFO buffers, thus reducing area and power consumption.
2Reliability
If a FIFO buffer is used to manage clock phase differences between subsystems, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent removes the power-consuming FIFO buffer component by implementing direct phase-differential data transmission. The transmitting subsystem detects phase relationships and adjusts transmission timing accordingly, eliminating the continuous power consumption associated with FIFO buffer operation while ensuring reliable data transfer between clock domains.
Solution Approach 2:
The system changes from static buffering to dynamic parameter adjustment by detecting phase differences and selecting appropriate transmission edges. This parameter-based approach allows reliable communication without the continuous power consumption of FIFO buffers, as data is transmitted directly with timing adjusted based on real-time phase detection.
3Area of stationary object
If data transmission timing is adjusted based on detected phase differences, then area consumption is reduced by eliminating FIFO buffers, but the complexity of detecting and managing phase differences increases
Solution Approach 1:
The patent introduces a phase detection mechanism as an intermediary between the transmitting and receiving subsystems. This detector monitors the phase relationship between clock signals and provides control information to the transmitting subsystem, enabling automatic adjustment of data transmission timing without requiring complex manual timing management or large buffering infrastructure.
Solution Approach 2:
The system implements feedback through phase detection, where the detected phase difference information is fed back to control the data transmission timing. This closed-loop approach automatically adjusts transmission edges based on real-time phase relationships, simplifying the overall system architecture compared to FIFO buffers while managing the complexity through automated feedback control.
4Use of energy by stationary object
If FIFO buffers are eliminated in favor of direct data transmission with phase detection, then power consumption and area are reduced, but the difficulty of detecting and measuring phase differences arises
Solution Approach 1:
The patent employs a phase detection circuit as an intermediary that simplifies the measurement of phase differences between clock signals. This detector provides processed phase difference information to the transmitting subsystem, making the detection and measurement tasks manageable while enabling the power-efficient direct transmission architecture without FIFO buffers.
Data Source
AI summary
An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.