Clock Edge Dithering Circuit for Harmonic Interference Reduction
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Solution Overview
Problem
Existing circuits for receiving radio signals face interference from harmonics generated by digital elements, which degrade input sensitivity due to the high amplitude of spectral portions in the receiving band.
Innovation Solution
A monolithically integrated semiconductor chip circuit incorporating a random event generator and a settable delay device that introduces a quasi-random time offset in clock signal edges, reducing harmonic interference by setting discrete delay values based on random signals generated by the event generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital elements are used for information processing with a clock signal, then synchronization and information processing capability are improved, but harmonics are generated that cause interference in the receiving band
Solution Approach 1:
The patent converts the harmful harmonic interference into a beneficial effect by intentionally generating a dither signal that mimics the spectral characteristics of the digital harmonics. This dither signal, when added to the clock signal, creates a randomized timing pattern that spreads the harmonic energy across a wider frequency range, thereby reducing the peak interference amplitude in the receiving band while maintaining the necessary synchronization functionality.
Solution Approach 2:
The patent changes the timing parameters of the clock signal by superimposing a dither signal with varying amplitude and frequency characteristics. This parameter modification randomizes the clock edge timing, which transforms the concentrated harmonic spectrum into a dispersed spectrum, reducing interference in specific frequency bands while preserving the overall clocking function for digital synchronization.
2Object-generated harmful factors
If the delay of clock signal edges is adjusted to reduce harmonic interference, then interference amplitude in the receiving band is reduced, but timing precision and synchronization accuracy may be affected
Solution Approach 1:
The patent implements a dynamic delay mechanism where the delay amount is not fixed but varies over time according to a dither signal. This dynamic adjustment continuously changes the timing of clock edges in a pseudorandom pattern, which spreads the spectral energy of harmonics across different frequencies and time instances, reducing peak interference while maintaining adequate timing precision through the controlled nature of the dither signal.
Data Source
AI summary
A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.