Clock Edge Detection Circuit for Duty Cycle Calibration
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Solution Overview
Problem
Existing electronic circuits face challenges in generating a reference clock with a 50% duty cycle due to manufacturing process variations and limited design resources, lacking effective calibration methods to correct clock skew.
Innovation Solution
A clock edge detection device and method that detects positive and negative edges of a target clock, using a delay circuit, register circuit, positive and negative edge detection circuits, and a calculation circuit to determine the duty cycle for clock skew calibration and design reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a frequency synthesizer generates a reference clock, then the reference clock is produced for circuit operation, but the duty cycle deviates from 50% due to manufacturing process variation
Solution Approach 1:
The patent applies preliminary action by pre-installing a duty cycle calibration function during the frequency synthesizer design phase. This calibration function proactively compensates for manufacturing variations before they affect operation, ensuring accurate 50% duty cycle output without requiring post-manufacturing adjustments.
Solution Approach 2:
The patent implements feedback by using detection circuits to monitor the actual duty cycle of the generated reference clock and feed this information back to the frequency synthesizer. This feedback loop enables real-time adjustment of the duty cycle to maintain precision despite manufacturing variations.
2Ease of manufacture
If design resources are limited, then cost is reduced, but the frequency synthesizer lacks preinstalled calibration function
Solution Approach 1:
The patent applies segmentation by dividing the frequency synthesizer into modular functional blocks, with the duty cycle calibration function as a separate, independently configurable module. This allows the calibration capability to be added or removed based on specific application requirements, optimizing design resources while maintaining precision when needed.
3Device complexity
If duty cycle is not calibrated, then device complexity is reduced, but clock skew calibration cannot be performed
Solution Approach 1:
The patent introduces an intermediary duty cycle detection circuit that measures the actual duty cycle and provides this information to the frequency synthesizer. This intermediary component enables clock skew calibration without requiring complex integrated calibration mechanisms, maintaining simplicity while achieving accuracy.
Data Source
AI summary
The present invention discloses a clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising: a delay circuit for receiving the target clock and transmitting it; a register circuit coupled to the delay circuit for recording and outputting plural target clock levels in accordance with a working clock; a positive edge detection circuit including a plurality of positive edge detectors coupled to the register circuit for detecting the positive edge of the target clock; and a negative edge detection circuit including a plurality of negative edge detectors coupled to the register circuit for detecting the negative edge of the target clock, wherein the positive edge detection circuit is operable to perform a logic operation to the target clock levels while the negative edge detection circuit is operable to perform a different logic operation to the target clock levels.