Clock-Edge Modulated Serial Link for DC-Balanced Signal Transmission
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Solution Overview
Problem
Conventional mobile device interfaces require multiple parallel channels for clock, data, and control signals, leading to high power consumption, hardware costs, and excessive electromagnetic radiation, with dedicated clock channels increasing costs and reducing flexibility in transmission bandwidth.
Innovation Solution
A single direct current balanced differential channel is used for transmitting clock, data, and control signals through clock edge modulation, which reduces power consumption by eliminating the need for a dedicated clock channel and employs voltage-mode drivers and a delay-locked loop for robust data recovery in high jitter environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple parallel channels are used for clock, data, and control signals, then signal transmission reliability is improved, but power consumption increases and hardware complexity increases
Solution Approach 1:
The patent combines clock, data, and control signals into a single serial channel using clock-edge modulation. The clock signal edge transitions encode data bits, while DC balancing control signals maintain signal integrity. This merging eliminates the need for separate dedicated clock and control channels, reducing power consumption while maintaining reliable transmission through the unified channel.
Solution Approach 2:
The single serial channel performs multiple functions: transmitting clock signals, data signals, and control signals simultaneously. The clock-edge modulated channel serves as a universal transmission medium that replaces multiple specialized parallel channels, achieving both clock and data transmission along with DC balancing control in one channel.
2Reliability
If multiple parallel channels are used for clock, data, and control signals, then signal transmission reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple parallel channels into a single serial channel that carries clock, data, and control signals. This consolidation reduces the number of physical channels and associated hardware components, simplifying the overall device structure while maintaining transmission reliability through the clock-edge modulation scheme.
3Stability of the object's composition
If a dedicated clock channel is used, then clock signal transmission stability is improved, but hardware cost increases and flexibility decreases
Solution Approach 1:
The patent extracts the clock signal transmission function from a dedicated clock channel and integrates it into the data channel through clock-edge modulation. The clock signal stability is maintained by using the edge transitions of the modulated clock signal for data sampling, eliminating the need for a separate dedicated clock channel and reducing hardware cost.
4Stability of the object's composition
If a dedicated clock channel is used, then clock signal transmission stability is improved, but adaptability decreases
Solution Approach 1:
The single serial channel serves multiple purposes: transmitting clock signals, data, and control signals. This universal channel provides flexibility in transmission bandwidth allocation while maintaining clock signal stability through the clock-edge modulation scheme, allowing adaptive bandwidth allocation for different transmission needs.
Data Source
AI summary
A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.