Clock Edge Throttling for ASIC Power and Thermal Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods fail to accurately monitor and throttle power consumption in hardware-based machine learning systems like ASICs, leading to inaccurate power management and unintended thermal issues due to sudden power surges, which can exceed system capabilities.
Innovation Solution
A hardware-based programmable architecture that directly measures power consumption and adjusts it to fit a desired power profile by modifying clock pulses without changing frequency, using a power measurement engine, power throttling signal generator, and power throttling engine to squash clock edges, thereby reducing power and thermal loads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock frequency is changed to throttle power consumption, then power consumption is reduced, but unintended consequences occur in other parts of the chip
Solution Approach 1:
The patent segments the clock signal into individual clock edges that can be independently controlled. Instead of changing the entire clock frequency, the system selectively removes specific clock edges (throttling) while maintaining the nominal clock frequency. This allows power consumption to be reduced without affecting other chip components that rely on the stable clock frequency, thereby resolving the contradiction between power reduction and operational stability.
Solution Approach 2:
The patent applies local quality by making the clock signal non-uniform - specifically removing certain rising or falling edges - while maintaining the overall clock frequency. This localized modification to the clock signal waveform allows power throttling in the power delivery network without disrupting the timing and frequency requirements of other chip components, thus resolving the contradiction between reducing power consumption and maintaining chip reliability.
2Productivity
If power delivery is increased during high chip activity, then performance is maintained, but thermal generation exceeds system support
Solution Approach 1:
The patent implements dynamic power throttling by continuously monitoring power consumption and dynamically adjusting the clock edge removal pattern in real-time. When thermal generation exceeds system support, the system dynamically removes additional clock edges to reduce power delivery, thereby maintaining thermal safety while preserving maximum possible performance. This dynamic adjustment resolves the contradiction between maintaining productivity and controlling temperature.
Solution Approach 2:
The patent employs feedback control by monitoring power consumption and thermal conditions, then using this information to adjust the clock throttling level. The power management integrated circuit (PMIC) receives feedback about power draw and thermal status, and accordingly modifies the clock signal to remove appropriate edges, creating a closed-loop system that balances performance and thermal generation, thus resolving the contradiction between productivity and temperature control.
3Ease of operation
If power consumption is inferred from chip activity, then power management is implemented, but accuracy is insufficient
Solution Approach 1:
The patent introduces an intermediary measurement approach by using a power management integrated circuit (PMIC) with a current sense amplifier to directly measure power consumption through the power delivery network, rather than inferring it from chip activity metrics. This intermediary measurement system provides accurate real-time power data, resolving the contradiction between ease of power management and measurement precision by providing reliable power information for control decisions.
Data Source
AI summary
A power throttling engine includes a register configured to receive a power throttling signal. The power throttling engine further includes a decoder configured to generate a vector based on a value of the power throttling signal. The value of the power throttling signal is an amount of power throttling of a device. The power throttling engine further includes a clock gating logic configured to receive the vector and further configured to receive a clocking signal. The clock gating logic is configured to remove clock edges of the clocking signal based on the vector to generate a throttled clocking signal.