Clock Edge Detection Circuit for Stable Pulse Width Under PVT Variation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Precise detection of clock signal edges in semiconductor apparatuses is challenging due to process, voltage, and temperature variations, as well as intrinsic transistor characteristics, which affects synchronization and operating speed.
Innovation Solution
A semiconductor apparatus with first and second edge detection signal generators that generate complementary edge detection signals by gating input and inverted signals based on delayed control signals, and combine these signals to produce an output clock signal, ensuring accurate edge detection and consistent pulse widths despite PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single edge detection circuit is used to detect clock signal edges, then the device complexity is low, but the measurement precision of edge detection deteriorates due to PVT variations and transistor characteristics
Solution Approach 1:
The edge detection function is divided into two separate circuits: a first edge detection circuit that detects rising edges using the input clock signal, and a second edge detection circuit that detects falling edges using the complementary clock signal. Each circuit is optimized for its specific detection task, improving overall precision while maintaining reasonable complexity
Solution Approach 2:
Each edge detection circuit is designed with specific local characteristics optimized for its detection purpose. The first circuit uses the input clock signal with specific gating control for rising edge detection, while the second circuit uses the complementary signal for falling edge detection, allowing each to operate at optimal performance for its specific function
2Productivity
If high frequency clock signals are used to increase operating speed, then the productivity increases, but the measurement precision of edge detection worsens due to narrow pulse widths making edges harder to detect accurately
Solution Approach 1:
The complementary clock signal is generated in advance through a differential clock generator before the edge detection process. This preliminary generation of the complementary signal ensures that both rising and falling edge detection circuits have the necessary input signals available, allowing accurate detection even at high frequencies where pulse widths are narrow
Solution Approach 2:
The complementary clock signal acts as an intermediary that enables accurate detection of falling edges. By having both the input clock signal and its complementary version available, the system can detect both rising and falling edges with equal precision, maintaining measurement accuracy at high operating frequencies
Data Source
AI summary
A semiconductor apparatus includes first and second edge detection signal generators. The first edge detection signal generator may generate a first edge detection signal by gating an input signal and its inverted signal based on a first gating control signal, generated by delaying the input signal, and output the first edge detection signal to an output node. The second edge detection signal generator may generate a second edge detection signal by gating a complementary signal of the input signal and its inverted signal based on a second gating control signal, generated by delaying the complementary signal, and output the second edge detection signal to the output node. An output signal may be generated at the output node.