Dynamic Clock Edge Selection for Read Data Recovery

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Solution Overview

Problem

Conventional master-slave interfaces face challenges in recovering read data due to delays and variability, especially when delays are long or highly variable, leading to inadequate data recovery.

Innovation Solution

A dynamic clock edge selection method and system that allows the master to choose between the rising and falling edges of a clock signal for read data recovery, using an edge selector and data sampler to determine the optimal edge based on the internal clock signal and read signal, enabling flexible and adaptive data recovery.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fixed clock edge recovery is used, then the system is simple to implement, but data recovery fails when delays are long or highly variable

Engineering Contradiction:
Improvedata recovery reliabilityVSAvoidclock edge selection mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system dynamically selects between rising and falling clock edges based on the actual delay characteristics of each transaction. The master controller monitors the timing of read data arrival and adaptively chooses the appropriate clock edge for sampling, transforming a static recovery mechanism into a dynamic one that responds to varying delay conditions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the sampling parameter (clock edge selection) based on the delay characteristics of the interface. By switching between different clock edges (rising or falling) depending on the measured delay, the system adapts to varying transaction conditions without requiring fundamental changes to the bus protocol.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If interface tuning is used to handle delays, then data recovery may succeed for small delay ranges, but the solution becomes inadequate when delays are too long or highly variable

Engineering Contradiction:
Improveread data recoveryVSAvoiddelay range accommodation
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

Instead of tuning fixed interface parameters, the system changes the sampling clock edge parameter dynamically. This allows the master to accommodate a wide range of delay values by selecting the appropriate clock edge that aligns with the delayed data arrival, providing adaptability across varying delay conditions.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system transitions from static interface tuning to dynamic clock edge selection. The master controller continuously adapts its sampling strategy based on real-time observation of data arrival timing, enabling reliable recovery across a broad range of delay scenarios rather than being limited to a narrow tuned range.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If a single clock edge is used for data recovery, then the recovery mechanism is simple, but it cannot handle variable delays effectively

Engineering Contradiction:
Improvedelay variability handlingVSAvoidclock edge selection logic
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system employs dynamic clock edge selection where the master controller chooses between rising and falling edges based on the observed delay characteristics of each transaction. This dynamic approach provides adaptability to variable delays while keeping the selection logic relatively simple, relying on timing observation rather than complex decision mechanisms.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7519789B1Method and system for dynamically selecting a clock edge for read data recovery
Publication Date: 2009.04.14 NAT SEMICON CORP
  • US7519789B1 patent drawing
  • US7519789B1 patent drawing
  • US7519789B1 patent drawing

AI summary

A method for dynamically selecting a clock edge for recovering read data received from a slave at a master is provided that includes determining whether an internal clock signal is high when a first bit of read data is received at the master. One of a falling edge and a rising edge of the internal clock signal are selected for recovering the read data based on the determination of whether the internal clock signal is high when the first bit of read data is received at the master.