Clock Edge Selection Circuit That Corrects Duty Cycle Distortion
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Solution Overview
Problem
Circuits often suffer from duty cycle distortion in clock signals, which degrades system performance, especially in high-speed I/O receivers where even and odd data bits need uniform sampling, and existing edge selection techniques may introduce runt pulses or fail to correct duty cycles effectively.
Innovation Solution
The implementation of a circuit comprising a multiplexer and an edge-triggered flip-flop that selectively outputs one of multiple input clock signals based on the logic level of the output clock signal, ensuring the output clock transitions coincide with the rising edges of the input clocks, thereby correcting duty cycle distortion and avoiding runt pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If edge selection circuits are used to synthesize output clock from two input clock signals, then the output clock can transition on every useful transition of the input clocks, but duty cycle distortion occurs in the output clock signal
Solution Approach 1:
The patent introduces an intermediary duty cycle correction circuit between the edge selection circuit and the output register. This correction circuit receives the distorted duty cycle clock signal, processes it through additional logic gates and registers, and outputs a corrected clock signal with proper 50% duty cycle to the output register, thereby eliminating the duty cycle distortion while preserving the edge selection functionality
Solution Approach 2:
The patent changes the temporal parameters of the clock signal by introducing controlled delays and hold times in the correction circuit. By strategically positioning register clocks and data holds at specific time intervals relative to the input clock edges, the circuit transforms the distorted duty cycle waveform into a properly timed signal with equal high and low periods
2Stability of the object's composition
If complementary clocks are processed by identical circuits, then their outputs may have matched duty cycles, but the time spacing from rising edge of one output to rising edge of other output may not be exactly one half clock period
Solution Approach 1:
The patent employs feedback mechanisms where the output of the correction circuit feeds back into the timing control of subsequent stages. The correction circuit monitors the actual timing relationships and adjusts the positioning of register clocks and data holds to ensure that the time spacing between rising edges of complementary outputs is exactly one half clock period, while maintaining duty cycle consistency
3Extent of automation
If existing edge selection techniques are used, then clock signal transitions can be captured, but runt pulses are introduced which degrade system performance
Solution Approach 1:
The patent applies beforehand cushioning by designing the correction circuit to anticipate and prevent the formation of runt pulses. The circuit incorporates minimum pulse width enforcement through the timing relationships of registers and logic gates, ensuring that any selected clock edge produces a properly sized output pulse before it can reach downstream circuits, thereby protecting signal integrity
Data Source
AI summary
Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.